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IDT79R3500 Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT79R3500 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 16 page IDT79R3500 RISC CPU PROCESSOR RISCore MILITARY AND COMMERCIAL TEMPERATURE RANGES Exceptions/Enables/Modes FGR1 FGR3 FGR5 FGR27 FGR29 FGR31 FGR0 FGR2 FGR4 FGR26 FGR28 FGR30 63 32 31 0 General Purpose Registers (FGR/FPR) 31 0 Control/Status Register 31 0 Implementation/Revision Register 2871 drw 03 Figure 3. FPA Registers Instruction Set Overview All IDT79R3500 instructions are 32 bits long, and there are only three instruction formats. This approach simplifies instruction decoding, thus minimizing instruction execution time. The IDT79R3500 processor initiates a new instruction on every run cycle, and is able to complete an instruction on almost every clock cycle. The only exceptions are the Load instructions and Branch instructions, which each have a single cycle of latency associated with their execution. Note, how- ever, that in the majority of cases the compilers are able to fill these latency cycles with useful instructions which do not require the result of the previous instruction. This effectively eliminates these latency effects. The actual instruction set of the CPU was determined after extensive simulations to determine which instructions should be implemented in hardware, and which operations are best synthesized in software from other basic instructions. This methodology resulted in the IDT79R3500 having the highest performance of any available microprocessor. The IDT79R3500 instruction set can be divided into the following groups: • Load/Store instructions move data between memory and general registers. They are all I-type instructions, since the only addressing mode supported is base register plus 16- bit, signed immediate offset. The Load instruction has a single cycle of latency, which means that the data being loaded is not available to the instruction immediately after the load instruction. The compiler will fill this delay slot with either an instruction which is not dependent on the loaded data, or with a NOP instruction. There is no latency associated with the store instruction. Loads and Stores can be performed on byte, half-word, word, or unaligned word data (32-bit data not aligned on a modulo-4 address). The CPU cache is constructed as a write-through cache. • Computational instructions perform arithmetic, logical and shift operations on values in registers. They occur in both R-type (both operands and the result are registers) and I-type (one operand is a 16-bit immediate) formats. FP computational instructions perform arithmetic operations on floating point values in the FPA registers. Note that computational instructions are three operand instructions; that is, the result of the operation can be stored into a different register than either of the two operands. This means that operands need not be overwritten by arithmetic operations. This results in a more efficient use of the large register set. • Conversion instructions perform conversion operations on the floating point values in the FPA registers. • Compare intructions perform comparisons of the contents of FPA registers and set a condition bit based on the results. The result of the compare operations is tied directly to Cp Cond (1) for software testing. • Jump and Branch instructions change the control flow of a program. Jumps are always to a paged absolute address formed by combining a 26-bit target with four bits of the Program counter (J-type format, for subroutine calls), or 32-bit register byte addresses (R-type, for returns and Figure 4. IDT79R3500 Instruction Formats I-Type (Immediate) 31 25 20 15 26 21 16 0 op rs rt immediate J-Type (Jump) 31 25 26 0 op target R-Type (Register) 31 25 20 15 26 21 16 6 op rs rt 10 11 5 0 rd re funct 2871 drw 04 |
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