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IDT72210L15TCB Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT72210L15TCB
Description  CMOS SyncFIFOO 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72210L15TCB Datasheet(HTML) 1 Page - Integrated Device Technology

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CMOS SyncFIFO
64 x 8, 256 x 8, 512 x 8,
1024 x 8, 2048 x 8 and 4096 x 8
IDT72420
IDT72200
IDT72210
IDT72220
IDT72230
IDT72240
FEATURES:
• 64 x 8-bit organization (IDT72420)
• 256 x 8-bit organization (IDT72200)
• 512 x 8-bit organization (IDT72210)
• 1024 x 8-bit organization (IDT72220)
• 2048 x 8-bit organization (IDT72230)
• 4096 x 8-bit organization (IDT72240)
• 12 ns read/write cycle time (IDT72420/72200/72210)
• 15 ns read/write cycle time (IDT72220/72230/72240)
• Read and write clocks can be asynchronous or
coincidental
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Almost-empty and almost-full flags set to Empty+7 and
Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Produced with advanced submicron CMOS technology
• Available in 28-pin 300 mil plastic DIP and 300 mil
ceramic DIP
• For surface mount product please see the IDT72421/
72201/72211/72221/72231/72241 data sheet
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40OC to +85OC) is
available, tested to military electrical specifications
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
64 x 8
256 x 8
512 x 8
••
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
WCLK
RCLK
REN
D0 - D7
Q0 - Q7
RS
OE
FF
AF
AE
EF
WEN
2680 drw 01
Integrated Device Technology, Inc.
DESCRIPTION:
The
IDT72420/72200/72210/72220/72230/72240
SyncFIFO
™ are very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72420/72200/72210/72220/72230/72240 have a 64,
256, 512, 1024, 2048, and 4096 x 8-bit memory array, respec-
tively. These FIFOs are applicable for a wide variety of data
buffering needs, such as graphics, Local Area Networks
(LANs), and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a write
enable pin (WEN). Data is written into the Synchronous FIFO
on every clock when WEN is asserted. The output port is
controlled by another clock pin (RCLK) and a read enable pin
(REN). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
These Synchronous FIFOs have two end-point flags, Empty
(EF) and Full (FF). Two partial flags, Almost-Empty (AE) and
Almost-Full (AF), are provided for improved system control.
The partial ( AE) flags are set to Empty+7 and Full-7 for AE and
AF respectively.
The IDT72420/72200/72210/72220/72230/72240 are fabri-
cated using IDT’s high-speed submicron CMOS technology.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NOVEMBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2680/6
5.12
1


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