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IDT7M1002S40G Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT7M1002S40G Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 12 page IDT7M1002 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE MILITARY AND COMMERCIAL TEMPERATURE RANGES 7.02 9 TIMING WAVEFORM OF READ WITH BUSY BUSY BUSY BUSY BUSY (M/SSSSS ≥ VIH)(2) 2795 drw 11 ADDR L VALID tWC tWP tDW tDH tBDA tBDD tWDD tDDD (3) tAPS (1) MATCH MATCH VALID BUSY L DATAOUT L DATAIN R ADDR R R/ W R NOTES: 1. To ensure that the earlier of the two ports wins. 2. (L_ CS = R_ CS) ≤ VIL 3. OE ≤ VIL for the reading port. TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY (M/ SSSSS ≤ VIH)(1, 2) 2795 drw 12 ADDR L VALID tWC tWP tDW tDH tWDD tDDD MATCH MATCH VALID DATAOUT L DATAIN R ADDR R R/ W R NOTES: 1. BUSY input equals HIGH for the writing port. 2. (L_ CS = R_ CS) ≤ VIL |
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