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3.3V LOW SKEW PLL-BASED CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

9

CMMU

CMMU

CPU

CMMU

CMMU

CMMU

CMMU

CMMU

CPU

CMMU

CMMU

CMMU

PLL

2f

PLL

2f

CPU

CARD

CPU

CARD

CLOCK

@f

SYSTEM

CLOCK

SOURCE

FCT388915T

FCT388915T

DISTRIBUTE

CLOCK @f

CLOCK @2f

at point of use

MEMORY

CONTROL

PLL

2f

MEMORY

CARDS

CLOCK @2f

at point of use

FCT388915T

Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication

and Low Board-to-Board skew

FCT388915T System Level Testing Functionality

When the PLL_EN pin is LOW, the PLL is bypassed and the

FCT388915T is in low frequency "test mode". In test mode

(with FREQ_SEL HIGH), the 2Q output is inverted from the

selected SYNC input, and the Q outputs are divide-by-2

(negative edge triggered) of the SYNC input, and the Q/2

output is divide-by-4 (negative edge triggered).

With

FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,

the Q outputs divide-by-4, and the Q/2 output divide-by-8.

These relationships can be seen in the block diagram. A

recommended test configuration would be to use SYNC0 or

SYNC1 as the test clock input, and tie PLL_EN and REF_SEL

together and connect them to the test select logic.

This functionality is needed since most board-level testers

run at 1 MHz or below, and theFCT 388915T cannot lock onto

that low of an input frequency. In the test mode described

above, any test frequency test can be used.

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