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March 28, 2000

© 2000 Integrated Device Technology, Inc.

DSC 3149/3

%ORFN#'LDJUDP

%ORFN#'LDJUDP

%ORFN#'LDJUDP

%ORFN#'LDJUDP

The IDT logo is a registered trademark and ORION, RC4600, RC4650, RV4650, RC4700, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.

352 M IP S 64 -b it C P U

64-bit register file

64-b it ad der

S tore A ligner

L ogic U nit

L oad aligner

H igh-P erform an ce

In teger M u ltiply

FP register file

FP A dd/Sub/C vt/

Pack /U npack

F P M ultiply

89M F L O P S Sin gle-P re cision F PA

Div/S qrt

32-/64-b it

S y nc hr on iz e d

S y ste m In te r fa c e

A d dress Tran slation/

Cache Attribu te Control

E xception M anagem ent

Functions

System C on trol C oprocesso r

Data Cach e

Data Cache

Instru ction B u s

Control Bus

Data B u s

Set A

(L ockable)

Set B

In stru ctio n C a ch e

Set B

Instru ction C ach e

Set A

(L ock able)

Low-Cost 64-bit

RISController

w/DSP Capability

)HDWXUH

)HDWXUH

)HDWXUH

)HDWXUHVVVV

–

64-bit integer operations

–

64-bit registers

–

100MHz, 133MHz, 150 MHz, 180MHz, 200MHz and 267MHz

operation frequencies

–

133.5 Million Integer Multiply-Accumulate Operations/sec @

267 MHz

–

133.5 M Mul-Add/second at 267MHz

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89 MFL0P/s at 250MHz

–

>640,000 dhrystone (2.1)/sec capability at 267MHz

(352 dhrystone MIPS)

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64-bit, 267 MHz integer CPU

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8KB instruction cache; 8KB data cache

–

Integer multiply unit with 133.5M Mul-Add/sec

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Active power management powers-down inactive units

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Standby mode

Family

–

Separate 8kB Instruction and 8kB Data caches

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Over 3200MB/sec bandwidth from internal caches

–

2-set associative

–

Write-back and write-through support

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Cache locking to facilitate deterministic response

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System interface provides bandwidth up to 1000 MB/S

–

Direct interface to 32-bit wide or 64-bit wide systems

–

Synchronized to external reference clock for multi-master

operation

–

Socket compatible with IDT RC64475 and RC64575

–

Fast interrupt decode

Optional cache locking

refers to both