IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

6

NOTES:

7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback

configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges,

depending on whether FREQ_SEL is HIGH or LOW. Also it is possible to feed back the

Q5 output, thus creating a 180° phase shift between the SYNC

input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration.

8. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input, varies with process, temperature

and voltage. Measurements were made with a 10MHz SYNC input and Q/2 output as feedback. The phase measurements were made at 1.5V. The Q/

2 output was terminated at the FEEDBACK input with 100

Ω to VCC and 100Ω to ground. tPD measurements were made with the loop filter connection

shown below:

LF

External Loop

Filter

0.1

µFC1

Analog GND

3052 drw 04

FREQ_SEL

Level

Feedback

Output

Allowable SYNC Input

Corresponding 2Q Output

Frequency Range

Phase Relationship

of the Q Outputs

to Rising SYNC Edge

HIGH

Q/2

0

°

HIGH

Any Q (Q0-Q4)

0

°

HIGH

Q5

180

°

HIGH

2X_Q

0

°

LOW

Q/2

0

°

LOW

Any Q (Q0-Q4)

0

°

LOW

Q5

180

°

LOW

2X_Q

0

°

3052 tbl 09