IDT74FCT833BLB datasheet(2/8 Pages) IDT

Part #	IDT74FCT833BLB

Description	FAST CMOS PARITY BUS TRANSCEIVER

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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7.21

2

IDT54/74FCT833A/B

FAST CMOS PARITY BUS TRANSCEIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

DIP/SOIC/CERPACK

TOP VIEW

LCC

TOP VIEW

2557 tbl 01

PIN DESCRIPTION

Pin Name

I/O

Description

OER

I

RECEIVE enable input.

RI

I/O

8-bit RECEIVE data input/output.

ERR

O

Output from fault registers.

Register

detection of odd parity fault on rising clock

edge (CLK). A registered

ERR output

remains LOW until cleared. Open drain

output, requires pull up resistor.

CLR

I

Clears the fault register output.

TI

I/O

8-bit TRANSMIT data input/output.

PARITY

I/O

1-bit PARITY output.

OET

I

TRANSMIT enable input.

CLK

I

External clock pulse input for fault register

flag.

ERROR FLAG OUTPUT FUNCTION TABLE

(1,2)

Internal

Output

Inputs

To Device

Pre-State

Output

CLR

CLK

Point “P”

ERR

ERRn–1

ERR

Function

H

↑

H

Sample

H

↑

—

L

(1’s

H

↑

L

—

L

Capture)

L

—

H

Clear

NOTES:

2557 tbl 02

1.

OET is HIGH and OER is LOW.

2. H = HIGH

L = LOW

↑ = LOW-to-HIGH transition of clock

– = Don't Care or Irrelevant

5

6

7

8

9

10

11

12

GND

R1

R2

R3

1

2

3

4

24

23

22

21

20

19

18

17

Vcc

16

15

14

13

OE

P24-1,

D24-1,

S024-2

&

E24-1

T1

R4

R5

R6

T2

T3

T4

T5

CLK

CLR

OE

ERR

PARITY

T

T6

T7

T0

R

R7

R0

5

6

7

8

9

10

11

L28-1

25

24

23

22

21

20

19

12 13 14 15 16 17 18

43

2

1

28 27 26

INDEX

2557 drw 02

R2

R3

R4

R5

R6

T2

T3

T4

T5

T6

T7

R7

NC

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