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IDT54FCT88915TT70JB Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT54FCT88915TT70JB Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 11 page IDT54/74FCT88915TT 55/70/100/133 LOW SKEW PLL-BASED CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.7 9 CMMU CMMU CPU CMMU CMMU CMMU CMMU CMMU CPU CMMU CMMU CMMU PLL 2f PLL 2f CPU CARD CPU CARD CLOCK @f SYSTEM CLOCK SOURCE FCT88915TT FCT88915TT DISTRIBUTE CLOCK @f CLOCK @2f at point of use MEMORY CONTROL PLL 2f MEMORY CARDS CLOCK @2f at point of use FCT88915TT 3072 drw 10 FCT88915TT System Level Testing Functionality When the PLL_EN pin is LOW, the PLL is bypassed and the FCT88915TT is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divide-by-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divide-by-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8. These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. This functionality is needed since most board-level testers run at 1 MHz or below, and theFCT 88915TT cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used. Figure 3. Multiprocessing Application Using the FCT88915TT for Frequency Multiplication and Low Board-to-Board skew |
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