15.2

5

IDT7MP4045/7MP4145

256K x 32 CMOS STATIC RAM MODULE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1

(1)

TIMING WAVEFORM OF READ CYCLE NO. 2

(1,2,4)

TIMING WAVEFORM OF READ CYCLE NO. 3

(1,3,4)

OE

ADDRESS

CS

DATA OUT

2703 drw 07

2703 drw 08

ADDRESS

DATA VALID

PREVIOUS DATA VALID

2703 drw 06

CS

(5)

(5)

NOTES:

1.

WE is HIGH for Read Cycle.

2. Device is continuously selected.

3. Address valid prior to or coincident with

CS transition LOW.

4.

5. Transition is measured

±200mV from steady state. This parameter is guaranteed by design, but not tested.