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IDT79R3051E-20MJ Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT79R3051E-20MJ Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 23 page 5.3 4 IDT79R3051/79R3052 INTEGRATED RISControllers COMMERCIAL TEMPERATURE RANGE Clock Generation Unit The IDT79R3051 family is driven from a single input clock, capable of operating in a range of 40%-60% duty cycle. On chip, the clock generator unit is responsible for managing the interaction of the CPU core, caches, and bus interface. The clock generator unit replaces the external delay line required in IDT79R3000A and IDT79R3001 based applications. Instruction Cache The current family includes two different instruction cache sizes: the IDT79R3051 family (the IDT79R3051 and IDT79R3051E) feature 4KB of instruction cache, and the IDT79R3052 and IDT79R3052E each incorporate 8KB of Instruction Cache. For all four devices, the instruction cache is organized as a line size of 16 bytes (four words). This relatively large cache achieves a hit rate well in excess of 95% in most applications, and substantially contributes to the performance inherent in the IDT79R3051 family. The cache is implemented as a direct mapped cache, and is capable of caching instructions from anywhere within the 4GB physical address space. The cache is implemented using physical addresses (rather than virtual addresses), and thus does not require flushing on context switch. Data Cache All four devices incorporate an on-chip data cache of 2KB, organized as a line size of 4 bytes (one word). This relatively large data cache achieves hit rates well in excess of 90% in most applications, and contributes substantially to the perfor- mance inherent in the IDT79R3051 family. As with the instruc- tion cache, the data cache is implemented as a direct mapped physical address cache. The cache is capable of mapping any word within the 4GB physical address space. The data cache is implemented as a write through cache, to insure that main memory is always consistent with the internal cache. In order to minimize processor stalls due to data write operations, the bus interface unit incorporates a 4- deep write buffer which captures address and data at the processor execution rate, allowing it to be retired to main memory at a much slower rate without impacting system performance. Bus Interface Unit The IDT79R3051 family uses its large internal caches to provide the majority of the bandwidth requirements of the execution engine, and thus can utilize a simple bus interface connected to slow memory devices. The IDT79R3051 family bus interface utilizes a 32-bit address and data bus multiplexed onto a single set of pins. The bus interface unit also provides an ALE signal to de- multiplex the A/D bus, and simple handshake signals to process processor read and write requests. In addition to the read and write interface, the IDT79R3051 family incorporates a DMA arbiter, to allow an external master to control the external bus. The IDT79R3051 family incorporates a 4-deep write buffer to decouple the speed of the execution engine from the speed of the memory system. The write buffers capture and FIFO processor address and data information in store operations, and presents it to the bus interface as write transactions at the rate the memory system can accommodate. The IDT79R3051/52 read interface performs both single word reads and quad word reads. Single word reads work with a simple handshake, and quad word reads can either utilize the simple handshake (in lower performance, simple sys- tems) or utilize a tighter timing mode when the memory system can burst data at the processor clock rate. Thus, the system designer can choose to utilize page or nibble mode DRAMs (and possibly use interleaving), if desired, in high-perfor- mance systems, or use simpler techniques to reduce com- plexity. In order to accommodate slower quad-word reads, the IDT79R3051 family incorporates a 4-deep read buffer FIFO, so that the external interface can queue up data within the processor before releasing it to perform a burst fill of the internal caches. Depending on the cost vs. performance tradeoffs appropriate to a given application, the system design engineer could include true burst support from the DRAM to provide for high-performance cache miss processing, or uti- lize the read buffer to process quad word reads from slower memory systems. SYSTEM USAGE The IDT79R3051 family has been specifically designed to easily connect to low-cost memory systems. Typical low-cost memory systems utilize slow EPROMs, DRAMs, and applica- tion-specific peripherals. These systems may also typically contain large, slow Static RAMs, although the IDT79R3051 family has been designed to not specifically require the use of external SRAMs. Figure 5 shows a typical system block diagram. Transpar- ent latches are used to de-multiplex the IDT79R3051/52 address and data busses from the A/D bus. The data paths between the memory system elements and the R3051 family A/D bus is managed by simple octal devices. A small set of simple PALs can be used to control the various data path elements, and to control the handshake between the memory devices and the CPU. DEVELOPMENT SUPPORT The IDT79R3051 family is supported by a rich set of development tools, ranging from system simulation tools through prom monitor support, logic analysis tools, and sub- system modules. Figure 7 is an overview of the system development process typically used when developing IDT79R3051 family-based applications. The IDT79R3051 family is supported by power- ful tools through all phases of project development. These tools allow timely, parallel development of hardware and software for IDT79R3051/52 based applications, and include tools such as: • A program, Cache-3051, which allows the performance of an IDT79R3051 family based system to be modeled and understood without requiring actual hardware. |
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