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IDT74FCT162823ETPAB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT74FCT162823ETPAB Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 9 page IDT54/74FCT16823AT/BT/CT/ET, 162823AT/BT/CT/ET FAST CMOS 18-BIT REGISTER MILITARY AND COMMERCIAL TEMPERATURE RANGES 5.16 6 SWITCHING CHARACTERISTICS OVER OPERATING RANGE 2772 tbl 09 NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested. 5. This condition is guaranteed but not tested. FCT16823AT/162823AT FCT16823BT/162823BT Com'l. Mil. Com'l. Mil. Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit tPLH tPHL Propagation Delay xCLK to xQx CL = 50pF RL = 500 Ω 1.5 10.0 1.5 11.5 1.5 7.5 1.5 8.5 ns CL = 300pF(5) RL = 500 Ω 1.5 20.0 1.5 20.0 1.5 15.0 1.5 16.0 tPHL Propagation Delay x CLR to xQx CL = 50pF RL = 500 Ω 1.5 14.0 1.5 15.0 1.5 9.0 1.5 9.5 ns tPZH tPZL Output Enable Time x OE to xQx CL = 50pF RL = 500 Ω 1.5 12.0 1.5 13.0 1.5 8.0 1.5 9.0 ns CL = 300pF(5) RL = 500 Ω 1.5 23.0 1.5 25.0 1.5 15.0 1.5 16.0 tPHZ tPLZ Output Disable Time x OE to xQx CL = 5pF(5) RL = 500 Ω 1.5 7.0 1.5 8.0 1.5 6.5 1.5 7.0 ns CL = 50pF RL = 500 Ω 1.5 8.0 1.5 9.0 1.5 7.5 1.5 8.0 tSU Set-up Time HIGH or LOW xDx to xCLK CL = 50pF RL = 500 Ω 4.0 — 4.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW xDx to xCLK 2.0 — 2.0 — 1.5 — 1.5 — ns tSU Set-up Time HIGH or LOW x CLKEN to xCLK 4.0 — 4.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW x CLKEN to xCLK 2.0 — 2.0 — 0 — 0 — ns tW xCLK Pulse Width HIGH or LOW 7.0 — 7.0 — 6.0 — 6.0 — ns tW x CLR Pulse Width LOW 6.0 — 7.0 — 6.0 — 6.0 — ns tREM Recovery Time x CLR to xCLK 6.0 — 7.0 — 6.0 — 6.0 — ns tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 — 0.5 ns |
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