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IDT74FCT821CTL Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74FCT821CTL Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 9 page IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.21 1 Integrated Device Technology, Inc. 1 HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS The IDT logo is a registered trademark of Integrated Device Technology, Inc. IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT FEATURES: • Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT821T/FCT823T/FCT825T: – A, B, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) – Power off disable outputs permit “live insertion” DESCRIPTION: The FCT82xT series is built using an advanced dual metal CMOS technology. The FCT82xT series bus interface regis- ters are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The FCT821T are buffered, 10-bit wide versions of the popular FCT374T function. The FCT823T are 9-bit wide buffered registers with Clock Enable ( EN) and Clear (CLR) – ideal for parity bus interfacing in high-performance microprogrammed systems. The FCT825T are 8-bit buffered registers with all the FCT823T controls plus multiple enables ( OE1, OE2, OE3) to allow multi- user control of the interface, e.g., CS, DMA and RD/WR. They are ideal for use as an output port requiring high IOL/IOH. The FCT82xT high-performance interface family can drive large capacitive loads, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in high-impedance state. MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995 ©1995 Integrated Device Technology, Inc 6.21 DSC-4202/5 FUNCTIONAL BLOCK DIAGRAM D CP Q Q CL D CP Q Q CL D0 DN Y0 YN EN CLR CP OE 2567 drw 01 |
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