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28F002BC Datasheet(PDF) 10 Page - Intel Corporation |
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28F002BC Datasheet(HTML) 10 Page - Intel Corporation |
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10 / 37 page  28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY E 10 PRELIMINARY 1.5 Pin Descriptions Table 1. 28F002BC Pin Descriptions Symbol Type Name and Function A–1, A0–A17 INPUT ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. A-1 is used on the PSOP package only. A17 is used on the TSOP and PDIP packages. A9 INPUT ADDRESS INPUT: When A9 is at VHH, the signature mode is accessed. During this mode, A0 decodes between the manufacturer and device IDs. DQ0– DQ7 INPUT/ OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a program operation. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched during the write cycle. Outputs array, Intelligent Identifier and Status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high deselects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# input stages. OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command Register and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. RP# INPUT RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in deep power-down mode, locks, and unlocks the boot block from program/erase. When RP# is at logic high level (6.5V maximum), the boot block is locked and cannot be programmed or erased. When RP# = VHH (11.4V minimum ), the boot block is unlocked and can be programmed or erased. When RP# is at a logic low level the boot block is locked, the deep power-down mode is enabled and the WSM is reset—preventing any blocks from being programmed or erased. When RP# transitions from logic low to logic high, the flash memory enters the read array mode. VCC DEVICE POWER SUPPLY: 5.0V ± 10%, 5.0V ± 5% VPP PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block. When VPP < VPPLK all blocks are locked and memory contents cannot be altered. GND GROUND: For all internal circuitry. NC NO CONNECT: Pin may be driven or left floating. |
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