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28F008B3 Datasheet(PDF) 6 Page - Intel Corporation |
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28F008B3 Datasheet(HTML) 6 Page - Intel Corporation |
6 / 49 page SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E 6 PRELIMINARY 1.2 Product Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: VCC for read operation, VCCQ for output swing, and VPP for program and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design. All Smart 3 Advanced Boot Block flash memory products provide program/erase capability at 2.7V or 12V and read with VCC at 2.7V. Since many designs read from the flash memory a large percentage of the time, 2.7V VCC operation can provide substantial power savings. The 12V VPP option maximizes program and erase performance during production programming. The Smart 3 Advanced Boot Block flash memory products are high-performance devices with low power operation. The available densities for the byte-wide devices (x8) are a. 8-Mbit (8,388,608-bit) flash memory organized as 1 Mbyte of 8 bits each b. 16-Mbit (16,777,216-bit) flash memory organized as 2 Mbytes of 8 bits each. For word-wide devices (x16) see the Smart 3 Advanced Boot Block Word-Wide Flash Memory Family datasheet. The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details). The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby un- burdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or byte program completion and status. Program and erase automation allows program and erase operations to be executed using an industry- standard two-write command sequence to the CUI. Data writes are performed in byte increments. Each byte in the flash memory can be programmed independently of other memory locations; every erase operation erases all locations within a block simultaneously. Program suspend allows system software to suspend the program command in order to read from any other block. Erase suspend allows system software to suspend the block erase command in order to read from or program data to any other block. The Smart 3 Advanced Boot Block flash memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered immediately following the completion of a read cycle. When the CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. A deep power- down mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power-down is 1 µA typical (2.7V VCC). A minimum reset time of tPHQV is required from RP# switching high until outputs are valid to read attempts. With RP# at GND, the WSM is reset and Status Register is cleared. Section 3.5 contains additional information on using the deep power-down feature, along with other power consumption issues. The RP# pin provides additional protection against unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6). Refer to the DC Characteristics Table, Sections 5.1 and 6.1, for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 7.0, for read, program and erase performance specifications. 2.0 PRODUCT DESCRIPTION This section explains device pin description and package pinouts. |
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