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P28F010-120 Datasheet(PDF) 11 Page - Intel Corporation |
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P28F010-120 Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 30 page  28F010 290207 – 5 Bus Command Comments Operation Standby Wait for VPP Ramp to VPPH(1) Initialize Pulse-Count Write Set-up Data e 40H Program Write Program Valid AddressData Standby Duration of Program Operation (tWHWH1) Write Program(2) Data e C0H Stops Program Verify Operation(3) Standby tWHGL Read Read Byte to Verify Programming Standby Compare Data Output to Data Expected Write Read Data e 00H Resets the Register for Read Operations Standby Wait for VPP Ramp to VPPL(1) NOTES 1 See DC Characteristics for the value of VPPH and VPPL 2 Program Verify is only performed after byte program- ming A final readcompare may be performed (option- al) after the register is written with the Read command 3 Refer to principles of operation 4 CAUTION The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the de- vice Figure 5 28F010 Quick Pulse Programming Algorithm 11 |
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