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PA28F008S5-120 Datasheet(PDF) 10 Page - Intel Corporation |
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PA28F008S5-120 Datasheet(HTML) 10 Page - Intel Corporation |
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10 / 37 page  BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY E 10 PRODUCT PREVIEW 2.1 Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to VPPH1/2. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP ≤ VPPLK, memory contents cannot be altered. When high voltage is applied to VPP, the two-step block erase, program, or lock-bit configuration command sequences provides pro- tection from unwanted operations. All write functions are disabled when VCC voltage is below the write lockout voltage VLKO or when RP# is at VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.0 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Block information, identifier codes, or status register can be read independent of the VPP voltage. RP# can be at either VIH or VHH. The first task is to write the appropriate read-mode command (Read Array, Read Identifier Codes, or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power- down mode, the device automatically resets to read array mode. Four control pins dictate the data flow in and out of the component: CE#, OE#, WE#, and RP#. CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection control, and when active enables the selected memory device. OE# is the data output (DQ0–DQ7) control and when active drives the selected memory data onto the I/O bus. WE# must be at VIH and RP# must be at VIH or VHH. Figure 15 illustrates a read cycle. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ7 are placed in a high-impedance state. 3.3 Standby CE# at a logic-high level (VIH) places the device in standby mode which substantially reduces device power consumption. DQ0–DQ7 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the device continues functioning and consuming active power until the operation completes. 3.4 Deep Power-Down RP# at VIL initiates the deep power-down mode. In read mode, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RP# must be held low for time tPLPH. Time tPHQV is required after return from power-down until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI resets to read array mode, and the status register is set to 80H. During block erase, program, or lock-bit configuration, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. |
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