E28F010-65 datasheet(6/30 Pages) INTEL

Part #	E28F010-65

Description	1024K (128K x 8) CMOS FLASH MEMORY

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Manufacturer	INTEL [Intel Corporation]

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28F010

290207 – 4

Figure 4 28F010 in a 80C186 System

PRINCIPLES OF OPERATION

Flash-memory augments EPROM functionality with

in-circuit electrical erasure and reprogramming The

28F010 introduces a command register to manage

this new functionality The command register allows

for 100% TTL-level control inputs fixed power sup-

plies during erasure and programming and maxi-

mum EPROM compatibility

In the absence of high voltage on the VPP pin the

28F010 is a read-only memory Manipulation of the

external memory-control pins yields the standard

EPROM read standby output disable and Intelli-

gent Identifier operations

The same EPROM read standby and output disable

operations are available when high voltage is ap-

plied to the VPP pin In addition high voltage on VPP

enables erasure and programming of the device All

functions associated with altering memory con-

tentsIntelligent Identifier erase erase verify pro-

gram and program verifyare accessed via the

command register

Commands are written to the register using standard

microprocessor write timings

Register contents

serve as input to an internal state-machine which

controls the erase and programming circuitry Write

cycles also internally latch addresses and data

needed for programming or erase operations With

the appropriate command written to the register

standard microprocessor read timings output array

data access the Intelligent Identifier codes or out-

put data for erase and program verification

Integrated Stop Timer

Successive command write cycles define the dura-

tions of program and erase operations specifically

the program or erase time durations are normally

terminated by associated program or erase verify

commands An integrated stop timer provides simpli-

fied timing control over these operations thus elimi-

nating the need for maximum programerase timing

specifications Programming and erase pulse dura-

tions are minimums only When the stop timer termi-

nates a program or erase operation the device en-

ters an inactive state and remains inactive until re-

ceiving the appropriate verify or reset command

Write Protection

The command register is only active when VPP is at

high voltage Depending upon the application the

system designer may choose to make the VPP pow-

er supply switchableavailable only when memory

updates are desired When VPP e VPPL the con-

6

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