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TB28F008S3-150 Datasheet(PDF) 5 Page - Intel Corporation |
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TB28F008S3-150 Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 41 page  E BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY 5 PRELIMINARY 1.0 INTRODUCTION This datasheet contains 4-, 8-, and 16-Mbit Smart 3 FlashFile memory specifications. Section 1.0 provides a flash memory overview. Sections 2.0, 3.0, 4.0, and 5.0 describe the memory organization and functionality. Section 6.0 covers electrical specifications for commercial and extended temperature product offerings. Ordering information is provided in Section 7.0. Finally, the byte-wide Smart 3 FlashFile memory family documentation also includes application notes and design tools which are referenced in Section 8.0. 1.1 New Features The byte-wide Smart 3 FlashFile memory family maintains backwards-compatibility with Intel’s 28F008SA-L. Key enhancements include: • SmartVoltage Technology • Enhanced Suspend Capabilities • In-System Block Locking They share a compatible status register, software commands, and pinouts. These similarities enable a clean upgrade from the 28F008SA-L to byte-wide Smart 3 FlashFile products. When upgrading, it is important to note the following differences: • Because of new feature and density options, the devices have different device identifier codes. This allows for software optimization. • VPPLK has been lowered from 6.5 V to 1.5 V to support low VPP voltages during block erase, program, and lock-bit configuration operations. Designs that switch VPP off during read operations should transition VPP to GND. • To take advantage of SmartVoltage tech- nology, allow VPP connection to 3.3 V. For more details see application note AP-625, 28F008SC Compatibility with 28F008SA (order number 292180) . 1.2 Product Overview The byte-wide Smart 3 FlashFile memory family provides density upgrades with pinout compatibility for the 4-, 8-, and 16-Mbit densities. The 28F004S3, 28F008S3, and 28F016S3 are high-performance memories arranged as 512 Kbyte, 1 Mbyte, and 2 Mbyte of eight bits. This data is grouped in eight, sixteen, and thirty-two 64-Kbyte blocks which are individually erasable, lockable, and unlockable in- system. Figure 5 illustrates the memory organization. SmartVoltage technology enables fast factory programming and low power designs. Specifically designed for 3 V systems, Smart 3 FlashFile components support read operations at 2.7 V and 3.3 V VCC and block erase and program operations at 2.7 V, 3.3 V and 12 V VPP. The 12 V VPP option renders the fastest program performance which will increase your factory throughput. With the 2.7 V or 3.3 V VPP option, VCC and VPP can be tied together for a simple, low-power 2.7 V or 3 V design. In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP ≤ VPPLK. Internal VPP detection circuitry automatically configures the device for optimized block erase and program operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device’s 64-Kbyte blocks typically within 1.1 second (12 V VPP), independent of other blocks. Each block can be independently erased 100,000 times (1.6 million block erases per device). A block erase suspend operation allows system software to suspend block erase to read data from or program data to any other block. Data is programmed in byte increments typically within 7.6 µs (12 V VPP). A program suspend operation permits system software to read data or execute code from any other flash memory array location. |
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