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PA28F016S5-95 Datasheet(PDF) 11 Page - Intel Corporation

Part # PA28F016S5-95
Description  BYTE-WIDE SMART 5 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
Download  37 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

PA28F016S5-95 Datasheet(HTML) 11 Page - Intel Corporation

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E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
11
PRODUCT PREVIEW
000000
Block 0
Master Lock Configuration
000001
000002
000003
010000
010002
00FFFF
Device Code
Block 0 Lock Configuration
Manufacturer Code
Reserved For
Future Implementation
Block 1
Block 1 Lock Configuration
Reserved for
Future Implementation
01FFFF
Reserved for
Future Implementation
1F0000
1F0002
Block 31 Lock Configuration
Reserved for
Future Implementation
1FFFFF
Block 31
(Blocks 16 through 30)
(Blocks 8 through 14)
(Blocks 2 through 14)
070000
070002
Block 7
Block 7 Lock Configuration
Reserved for
Future Implementation
07FFFF
Reserved for
Future Implementation
0F0000
0F0002
Block 15
Block 15 Lock Configuration
Reserved for
Future Implementation
0FFFFF
8-Mbit
16-Mbit
4-Mbit
Reserved for
Future Implementation
Reserved for
Future Implementation
Figure 5. Device Identifier Code Memory Map
3.5
Read Identifier Codes
Operation
The read identifier codes operation outputs the
manufacturer
code,
device
code,
block
lock
configuration codes for each block, and master lock
configuration code (see Figure 5). Using the
manufacturer
and
device
codes,
the
system
software can automatically match the device with its
proper algorithms. The block lock and master lock
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
3.6
Write
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active
and OE# = VIH. The address and data needed to
execute a command are latched on the rising edge
of WE# or CE# (whichever goes high first).
Standard microprocessor write timings are used.
Figure 17 illustrates a write operation.
4.0
COMMAND DEFINITIONS
When the VPP voltage
≤ VPPLK, read operations
from the status register, identifier codes, or blocks
are enabled. Placing VPPH1/2 on VPP enables
successful block erase, program, and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these
commands.


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