E28F160S5-100 datasheet(5/50 Pages) INTEL

Part #	E28F160S5-100

Description	WORD-WIDE FlashFile MEMORY FAMILY

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E

28F160S5, 28F320S5

5

ADVANCE INFORMATION

1.0

INTRODUCTION

This datasheet contains Word-Wide FlashFile™

memory

(28F160S5,

28F320S5)

specifications.

Section 1 provides a flash memory overview.

Sections 2, 3, 4, and 5 describe the memory

organization and functionality. Section 6 covers

electrical specifications for extended temperature

product offerings.

1.1

New Features

The Word-Wide FlashFile memory family maintains

basic compatibility with Intel’s 28F016SA and

28F016SV. Key enhancements include:

• Common Flash Interface (CFI) Support

• Scaleable Command Set (SCS) Support

• S5 Technology

• Enhanced Suspend Capabilities

They share a compatible Status Register, basic

software commands, and pinout. These similarities

enable a clean migration from the 28F016SA or

28F016SV. When upgrading, it is important to note

the following differences:

• Because of new feature and density options,

the devices have different device identifier

codes. This allows for software optimization.

• New software commands.

• To take advantage of the 5V technology on the

28F160S5

and

28F320S5,

allow

VPP

connection

to

VCC.

The

28F160S5

and

28F320S5 FlashFile memories do not support a

12V VPP option.

1.2

Product Overview

The Word-Wide FlashFile memory family provides

density upgrades with pinout compatibility for the

16-

and

32-Mbit

densities.

They

are

high-

performance memories arranged as 1 Mword and

2 Mwords of 16 bits or 2 Mbyte and 4 Mbyte of

8 bits. This data is grouped in thirty-two and sixty-

four 64-Kbyte blocks that can be erased, locked,

and unlocked in-system. Figure 1 shows the block

diagram, and Figure 4 illustrates the memory

organization.

Specifically

designed

for

5V

systems,

the

28F160S5 and 28F320S5 support read and write

operation with VCC equal to VPP. Coupled with this

capability,

high

programming

performance

is

achieved through small,

highly-optimized write

buffer operations. Additionally, the dedicated VPP

pin gives complete data protection when VPP

≤

VPPLK.

A Common Flash Interface (CFI) permits OEM-

specified software algorithms to be used for entire

families of devices. This allows device-independent,

JEDEC

ID-independent,

and

forward-

and

backward-compatible

software

support

for

the

specified flash device families. Flash vendors can

standardize their existing interfaces for long-term

compatibility.

Scaleable Command Set (SCS) allows a single,

simple software driver in all host systems to work

with all SCS-compliant flash memory devices,

independent

of

system-level

packaging

(e.g.,

memory card, SIMM, or direct-to-board placement).

Additionally,

SCS

provides

the

highest

system/device data transfer rates and minimizes

device and system-level implementation costs.

A Command User Interface (CUI) serves as the

interface

between

the

system

processor

and

internal

device

operation.

A

valid

command

sequence written to the CUI

initiates

device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase, program, and lock-bit

configuration operations.

A block erase operation erases one of the device’s

64-Kbyte

blocks

typically

within

tWHQV2/EHQV2

independent of other blocks. Each block can be

independently erased 100,000 times. Block erase

suspend allows system software to suspend block

erase to read or write data from any other block.

Data is programmed in byte, word or page

increments. Program suspend mode enables the

system to read data or execute code from any other

flash memory array location.

The device incorporates two Write Buffers of 32

bytes (16 words) to allow optimum-performance

data

programming.

This

feature

can

improve

system program performance by up to eight times

over non-buffer programming.

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