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N28F010-120 Datasheet(PDF) 8 Page - Intel Corporation |
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N28F010-120 Datasheet(HTML) 8 Page - Intel Corporation |
8 / 30 page 28F010 With CE and OE at a logic low level raising A9 to high voltage VID (see DC Characteristics) acti- vates the operation Data read from locations 0000H and 0001H represent the manufacturer’s code and the device code respectively The manufacturer- and device-codes can also be read via the command register for instances where the 28F010 is erased and reprogrammed in the tar- get system Following a write of 90H to the com- mand register a read from address location 0000H outputs the manufacturer code (89H) A read from address 0001H outputs the device code (B4H) Write Device erasure and programming are accomplished via the command register when high voltage is ap- plied to the VPP pin The contents of the register serve as input to the internal state-machine The state-machine outputs dictate the function of the device The command register itself does not occupy an ad- dressable memory location The register is a latch used to store the command along with address and data information needed to execute the command The command register is written by bringing WE to a logic-low level (VIL) while CE is low Addresses are latched on the falling edge of WE while data is latched on the rising edge of the WE pulse Stan- dard microprocessor write timings are used Refer to AC Write Characteristics and the Erase Programming Waveforms for specific timing parameters COMMAND DEFINITIONS When low voltage is applied to the VPP pin the con- tents of the command register default to 00H en- abling read-only operations Placing high voltage on the VPP pin enables read write operations Device operations are selected by writing specific data patterns into the command reg- ister Table 3 defines these 28F010 register commands Table 3 Command Definitions Command Cycles Req’d Bus First Bus Cycle Second Bus Cycle Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3) Read Memory 1 Write X 00H Read Intelligent Identifier 3 Write IA 90H Read IA ID Codes(4) Set-up EraseErase(5) 2 Write X 20H Write X 20H Erase Verify(5) 2 Write EA A0H Read X EVD Set-up ProgramProgram(6) 2 Write X 40H Write PA PD Program Verify(6) 2 Write X C0H Read X PVD Reset(7) 2 Write X FFH Write X FFH NOTES 1 Bus operations are defined in Table 2 2 IA e Identifier address 00H for manufacturer code 01H for device code EA e Erase Address Address of memory location to be read during erase verify PA e Program Address Address of memory location to be programmed Addresses are latched on the falling edge of the WE pulse 3 ID e Identifier Data Data read from location IA during device identification (Mfr e 89H Device e B4H) EVD e Erase Verify Data Data read from location EA during erase verify PD e Program Data Data to be programmed at location PA Data is latched on the rising edge of WE PVD e Program Verify Data Data read from location PA during program verify PA is latched on the Program command 4 Following the Read inteligent ID command two read operations access manufacturer and device codes 5 Figure 6 illustrates the Quick Erase Algorithm 6 Figure 5 illustrates the Quick Pulse Programming Algorithm 7 The second bus cycle must be followed by the desired command register write 8 |
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