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IDT79R3081E-40MJB Datasheet(PDF) 2 Page - Integrated Device Technology

Part # IDT79R3081E-40MJB
Description  RISController with FPA
Download  38 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT79R3081E-40MJB Datasheet(HTML) 2 Page - Integrated Device Technology

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IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
The R3051, which incorporates 4kB of instruction cache
and 2kB of data cache, but omits the TLB, and instead uses
a simpler virtual to physical address mapping.
The R3081E, which incorporates a 16kB instruction cache,
a 4kB data cache, and full function memory management
unit (MMU) including 64-entry fully associative Translation
Lookaside Buffer (TLB). The cache on the R3081E is user
configurable to an 8kB Instruction Cache and 8kB Data
Cache.
The R3081, which incorporates a 16kB instruction cache,
a 4kB data cache, but uses the simpler memory mapping
of the R3051/52, and thus omits the TLB. The cache on the
R3081 is user configurable to an 8kB Instruction Cache and
8kB Data Cache.
Figure 1 shows a block level representation of the functional
units within the R3081E. The R3081E could be viewed as the
embodiment of a discrete solution built around the R3000A
and R3010A. However, by integrating this functionality on a
single chip, dramatic cost and power reductions are achieved.
CPU Core
The CPU core is a full 32-bit RISC integer execution
engine, capable of sustaining close to single cycle execution.
The CPU core contains a five stage pipeline, and 32 orthogonal
32-bit registers. The R3081 uses the same basic integer
execution core as the entire R3051 family, which is the
R3000A implementation of the MIPS instruction set. Thus, the
R3081 family is binary compatible with the R3051, R3052,
R3000A, R3001, and R3500 CPUs. In addition, the R4000
represents an upwardly software compatible migration path to
still higher levels of performance.
The execution engine in the R3081 uses a five-stage
pipeline to achieve near single-cycle instruction execution
rates. A new instruction can be initiated in each clock cycle;
the execution engine actually processes five instructions
concurrently (in various pipeline stages). Figure 2 shows the
concurrency achieved in the R3081 execution pipeline.
System Control Co-Processor
The R3081 family also integrates on-chip the System
Control Co-processor, CP0. CP0 manages both the exception
handling capability of the R3081, as well as the virtual to
physical address mapping.
As with the R3051 and R3052, the R3081 offers two
versions of memory management and virtual to physical
address mapping: the extended architecture versions, the
R3051E, R3052E, and R3081E, incorporate the same MMU
as the R3000A. These versions contain a fully associative 64-
entry TLB which maps 4kB virtual pages into the physical
address space. The virtual to physical mapping thus includes
kernel segments which are hard-mapped to physical
addresses, and kernel and user segments which are mapped
page by page by the TLB into anywhere in the 4GB physical
address space. In this TLB, 8 pages can be “locked” by the
kernel to insure deterministic response in real-time applications.
Figure 3 illustrates the virtual to physical mapping found in the
R3081E.
INTRODUCTION
The IDT R3051 family is a series of high-performance 32-
bit microprocessors featuring a high-level of integration, and
targeted to high-performance but cost sensitive processing
applications. The R3051 family is designed to bring the high-
performance inherent in the MIPS RISC architecture into
low-cost, simplified, power sensitive applications.
Thus, functional units have been integrated onto the CPU
core in order to reduce the total system cost, rather than to
increase the inherent performance of the integer engine.
Nevertheless, the R3051 family is able to offer 43VUPS
performance at 50MHz without requiring external SRAM or
caches.
The R3081 extends the capabilities of the R3051 family, by
integrating additional resources into the same pin-out. The
R3081 thus extends the range of applications addressed by
the R3051 family, and allows designers to implement a single,
base system and software set capable of accepting a wide
variety of CPUs, according to the price/performance goals of
the end system.
In addition to the embedded applications served by the
R3051 family, the R3081 allows low-cost, entry level computer
systems to be constructed. These systems will offer many
times the performance of traditional PC systems, yet cost
approximately the same. The R3081 is able to run any
standard R3000A operation system, including ACE UNIX.
Thus, the R3081 can be used to build a low-cost ARC
compliant system, further widening the range of performance
solutions of the ACE Initiative.
An overview of this device, and quantitative electrical
parameters and mechanical data, is found in this data sheet;
consult the
"R3081 Family Hardware User's Guide" for a
complete description of this processor.
DEVICE OVERVIEW
As part of the R3051 family, the R3081 extends the offering
of a wide range of functionality in a compatible interface. The
R3051 family allows the system designer to implement a
single base system, and utilize interface-compatible processors
of various complexity to achieve the price-performance goals
of the particular end system.
Differences among the various family members pertain to
the on-chip resources of the processor. Current family members
include:
The R3052E, which incorporates an 8kB instruction cache,
a 2kB data cache, and full function memory management
unit (MMU) including 64-entry fully associative Translation
Lookaside Buffer (TLB).
The R3052, which also incorporates an 8kB instruction
cache and 2kB data cache, but does not include the TLB,
and instead uses a simpler virtual to physical address
mapping.
The R3051E, which incorporates 4kB of instruction cache
and 2kB of data cache, along with the full function MMU/
TLB of the R3000A.


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