REV. 0

AD1991

–7–

INA

INB

LEVEL SHIFTER

AND

SWITCH CONTROL

H-BRIDGE

AGND DGND

INPUT

TEST

CONTROL

PGND

A1

A2

B1

B2

C1

C2

D1

D2

INC

IND

CLK

RST/PDN

MUTE

CURRENT OVERLOAD

THERMAL SHUTDOWN

THERMAL WARNING

DATA LOSS

2

4

14

6

THERMAL PROTECTION

SHORT-CIRCUIT PROTECTION

MUTE CONTROL

n

OUTA

3

OUTB

3

OUTC

3

OUTD

3

Figure 4. Functional Block Diagram (1-Channel Mode)

EDGE SPEED AND NONOVERLAP SETTINGS

The AD1991 allows the user to select from one of eight different

edge speeds and from one of eight different nonoverlap times.

This allows the user to make a trade-off between distortion,

efficiency, overshooting at the outputs, and EMI. The following

sections describe the method used to program the settings.

Edge Speed

The edge speed is set by using the three pins,

ERR3, ERR2, and

INB, when

RST/PDN is low. The levels on the three pins are

latched by the rising edge of

RST/PDN. The latched value deter-

mines the edge speed thereafter, until

RST/PDN is brought low.

Table VI shows the appropriate logic levels for the corresponding

edge speeds. Note that INB is internally inverted, resulting in

the nonmonotonic sequence in Table VI.

Table VI. Edge Speed Settings

ERR3

ERR2

INB

Edge Speed

001

1 (Slowest Edge Speed)

000

2

011

3

010

4

101

5

100

6

111

7

110

8 (Fastest Edge Speed)

Nonoverlap Time

The nonoverlap time is set by using the three pins,

ERR1, ERR0,

and IND, when

RST/PDN is low. The levels on the three pins

are latched by the rising edge of

RST/PDN. The latched value

determines the nonoverlap time thereafter, until

RST/PDN is

brought low. Table VII shows the appropriate logic levels for

the corresponding nonoverlap times. Note that IND is internally

inverted, resulting in the nonmonotonic sequence in Table VII.

Note that

ERR3, ERR2, ERR1, and ERR0 are driven outputs

under normal operation and, therefore, should never be tied to a

dc voltage. The part contains internal 300 k

Ω pull-up resistors

to pull these pins high during reset. If it is desired to set them

low to achieve a particular edge speed or nonoverlap time, this

should be done by pulling them low through resistors between

10 k

Ω and 50 kΩ.

Table VII. Nonoverlap Time Settings

ERR1

ERR0

IND

Nonoverlap Time

00

11 (Shortest Nonoverlap Time)

00

0

2

01

1

3

01

0

4

10

1

5

10

0

6

11

1

7

11

08 (Longest Nonoverlap Time)