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376 Datasheet(PDF) 5 Page - Intel Corporation |
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376 Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 95 page  376 EMBEDDED PROCESSOR The following table lists a brief description of each pin on the 80376 The following definitions are used in these descriptions The named signal is active LOW I Input signal O Output signal IO Input and Output signal No electrical connection Symbol Type Name and Function CLK2 I CLK2 provides the fundamental timing for the 80376 For additional information see Clock in Section 41 RESET I RESET suspends any operation in progress and places the 80376 in a known reset state See Interrupt Signals in Section 41 for additional information D15–D0 IO DATA BUS inputs data during memory IO and interrupt acknowledge read cycles and outputs data during memory and IO write cycles See Data Bus in Section 41 for additional information A23–A1 O ADDRESS BUS outputs physical memory or port IO addresses See Address Bus in Section 41 for additional information WR O WRITEREAD is a bus cycle definition pin that distinguishes write cycles from read cycles See Bus Cycle Definition Signals in Section 41 for additional information DC O DATACONTROL is a bus cycle definition pin that distinguishes data cycles either memory or IO from control cycles which are interrupt acknowledge halt and instruction fetching See Bus Cycle Definition Signals in Section 41 for additional information MIO O MEMORY IO is a bus cycle definition pin that distinguishes memory cycles from inputoutput cycles See Bus Cycle Definition Signals in Section 41 for additional information LOCK O BUS LOCK is a bus cycle definition pin that indicates that other system bus masters are denied access to the system bus while it is active See Bus Cycle Definition Signals in Section 41 for additional information ADS O ADDRESS STATUS indicates that a valid bus cycle definition and address (WR DC MIO BHE BLE and A23–A1) are being driven at the 80376 pins See Bus Control Signals in Section 41 for additional information NA I NEXT ADDRESS is used to request address pipelining See Bus Control Signals in Section 41 for additional information READY I BUS READY terminates the bus cycle See Bus Control Signals in Section 41 for additional information BHE BLE O BYTE ENABLES indicate which data bytes of the data bus take part in a bus cycle See Address Bus in Section 41 for additional information HOLD I BUS HOLD REQUEST input allows another bus master to request control of the local bus See Bus Arbitration Signals in Section 41 for additional information 5 |
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