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PA28F200BX-T120 Datasheet(PDF) 11 Page - Intel Corporation |
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PA28F200BX-T120 Datasheet(HTML) 11 Page - Intel Corporation |
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11 / 48 page  28F200BX-TB 28F002BX-TB 21 28F200BX Memory Organization 211 BLOCKING The 28F200BX uses a blocked array architecture to provide independent erasure of memory blocks A block is erased independently of other blocks in the array when an address is given within the block ad- dress range and the Erase Setup and Erase Confirm commands are written to the CUI The 28F200BX is a random readwrite memory only erasure is per- formed by block 2111 Boot Block Operation and Data Protection The 16-Kbyte boot block provides a lock feature for secure code storage The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of pow- er failure or other disruption during code update This lock feature ensures absolute data integrity by preventing the boot block from being written or erased when RP is not at 12V The boot block can be erased and written when RP is held at 12V for the duration of the erase or program operation This allows customers to change the boot code when necessary while providing security when needed See the Block Memory Map section for address locations of the boot block for the 28F200BX-T and 28F200BX-B 2112 Parameter Block Operation The 28F200BX has 2 parameter blocks (8 Kbytes each) The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information The pa- rameter blocks can also be used to store additional boot or main code The parameter blocks however do not have the hardware write protection feature that the boot block has The parameter blocks pro- vide for more efficient memory utilization when deal- ing with parameter changes versus regularly blocked devices See the Block Memory Map section for ad- dress locations of the parameter blocks for the 28F200BX-T and 28F200BX-B 2113 Main Block Operation Two main blocks of memory exist on the 28F200BX (1 x 128 Kbyte block and 1 x 96-Kbyte block) See the following section on Block Memory Map for the address location of these blocks for the 28F200BX-T and 28F200BX-B products 212 BLOCK MEMORY MAP Two versions of the 28F200BX product exist to sup- port two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location The 28F200BX-T memory map is inverted from the 28F200BX-B memory map 2121 28F200BX-B Memory Map The 28F200BX-B device has the 16-Kbyte boot block located from 00000H to 01FFFH to accommo- date those microprocessors that boot from the bot- tom of the address map at 00000H In the 28F200BX-B the first 8-Kbyte parameter block re- sides in memory space from 02000H to 02FFFH The second 8-Kbyte parameter block resides in memory space from 03000H to 03FFFH The 96-Kbyte main block resides in memory space from 04000H to 0FFFFH The 128-Kbyte main block re- sides in memory space from 10000H to 1FFFFH (word locations) See Figure 7 (Word Addresses) 1FFFFH 128-Kbyte MAIN BLOCK 0FFFFH 10000H 96-Kbyte MAIN BLOCK 03FFFH 04000H 8-Kbyte PARAMETER BLOCK 02FFFH 03000H 8-Kbyte PARAMETER BLOCK 01FFFH 02000H 16-Kbyte BOOT BLOCK 00000H Figure 7 28F200BX-B Memory Map 11 |
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