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IDT74FCT825BPB Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT74FCT825BPB Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 8 page 7.19 6 IDT54/74FCT821/823/824/825A/B/C HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE NOTES: 2608 tbl* 08 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. IDT54/74FCT821A/ 823A/824A/825A IDT54/74FCT821B/ 823B/824B/825B IDT54/74FCT821C/ 823C/824C/825C Test Com'l. Mil. Com'l. Mil. Com'l. Mil. Parameter Description Conditions(1) Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tPLH tPHL Propagation Delay CP to Y I ( OE = LOW) CL = 50pF RL = 500 Ω — 10.0 — 11.5 — 7.5 — 8.5 — 6.0 — 7.0 ns CL = 300pF(3) RL = 500 Ω — 20.0 — 20.0 — 15.0 — 16.0 — 12.5 — 13.5 tSU Set-up Time HIGH or LOW D i to CP CL = 50pF RL = 500 Ω 4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW D I to CP 2.0 — 2.0 — 1.5 — 1.5 — 1.5 — 1.5 — ns tSU Set-up Time HIGH or LOW EN to CP 4.0 — 4.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns tH Hold Time HIGH or LOW EN to CP 2.0 — 2.0 — 0 — 0 — 0 — 0 — ns tPHL Propagation Delay, CLR to YI — 14.0 — 15.0 — 9.0 — 9.5 — 8.0 — 8.5 ns tREM Recovery Time CLR to CP 6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns tW CP Pulse Width HIGH or LOW 7.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns tW CLR Pulse Width LOW 6.0 — 7.0 — 6.0 — 6.0 — 6.0 — 6.0 — ns tPZH tPZL Output Enable Time OE to YI CL = 50pF RL = 500 Ω — 12.0 — 13.0 — 8.0 — 9.0 — 7.0 — 8.0 ns CL = 300pF(3) RL = 500 Ω — 23.0 — 25.0 — 15.0 — 16.0 — 12.5 — 13.5 tPHZ tPLZ Output Disable Time OE to YI CL = 5pF(3) RL = 500 Ω — 7.0 — 8.0 — 6.5 — 7.0 — 6.2 — 6.2 ns CL = 50pF RL = 500 Ω — 8.0 — 9.0 — 7.5 — 8.0 — 6.5 — 6.5 |
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