80960CA-16 datasheet(11/62 Pages) INTEL

Part #	80960CA-16

Description	SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

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Manufacturer	INTEL [Intel Corporation]

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SPECIAL ENVIRONMENT 80960CA-25 -16

Table 3 80960CA Pin DescriptionExternal Bus Signals

(Continued)

Name

Type

Description

BOFF

I

BUS BACKOFF

when asserted suspends the current access and causes

the bus pins to float When BOFF is deasserted the ADS signal is asserted

S(L)

on the next clock cycle and the access is resumed

H(Z)

R(Z)

HOLDA

O

HOLD ACKNOWLEDGE

indicates to a bus requestor that the processor has

relinquished control of the external bus When HOLDA is asserted the

S

external address bus data bus and bus control signals are floated HOLD

H(1)

BOFF HOLDA and BREQ are used together to arbitrate access to the

R(Q)

processor’s external bus by external bus agents Since the processor grants

HOLD requests and enters the Hold Acknowledge state even while RESET is

asserted the state of the HOLDA pin is independent of the RESET pin

BREQ

O

BUS REQUEST

is asserted when the bus controller has a request pending

BREQ can be used by external bus arbitration logic in conjunction with HOLD

S

and HOLDA to determine when to return mastership of the external bus to the

H(Q)

processor

R(0)

DC

O

DATA OR CODE

is asserted for a data request and deasserted for instruction

requests DC has the same timing as WR

S

H(Z)

R(Z)

DMA

O

DMA ACCESS

indicates whether the bus request was initiated by the DMA

controller DMA is asserted for any DMA request DMA is deasserted for all

S

other requests

H(Z)

R(Z)

SUP

O

SUPERVISOR ACCESS

indicates whether the bus request is issued while in

supervisor mode SUP is asserted when the request has supervisor privileges

S

and is deasserted otherwise SUP can be used to isolate supervisor code and

H(Z)

data structures from non-supervisor requests

R(Z)

11

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