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TB28F800B5T90 Datasheet(PDF) 5 Page - Intel Corporation |
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TB28F800B5T90 Datasheet(HTML) 5 Page - Intel Corporation |
5 / 38 page E SMART 5 BOOT BLOCK MEMORY FAMILY 5 ADVANCE INFORMATION 1.0 INTRODUCTION This datasheet contains specifications for 2-, 4-, and 8-Mbit Smart 5 boot block flash memories. Section 1.0 provides a feature overview. Sections 2.0, 3.0, and 4.0 describe the product and functionality. Section 5.0 details the electrical and timing specifications for both commercial and extended temperature operation. Finally, Sections 6.0 and 7.0 provide ordering and reference information. 1.1 New Features in the Smart 5 Memory Products The Smart 5 boot block flash memory family offers identical features with the BV/CV/BE/CE SmartVoltage products, except the Smart 5 boot block -B5 parts only support 5 V VCC read voltage. The following differences distinguish the Smart 5 boot block products from their predecessors: • A delay is required if the part is reset during an in-progress program or erase operation. • On the fly word-byte mode switching is no longer supported. Word-byte mode must be configured at power-up and remain stable during operation. • Write operations are no longer specified as WE#- or CE#-controlled in favor of a simpler “unified” write method, which is compatible with either of the old methods. 1.2 Product Overview The Smart 5 boot block memory family provides pinout-compatible flash memories at the 2-, 4-, and 8-Mbit densities. The 28F200B5, 28F400B5, and 28F800B5 can be configured to operate either in 16-bit or 8-bit bus mode, with the data divided into individually erasable blocks. The 28F004B5 provides 8-bit operation in a compact package. Table 1. Smart 5 Boot Block Family: Feature Summary Feature 28F200B5 28F400B5 28F800B5 28F004B5 Reference VCC Read Voltage 5 V ± 5%, 5 V ± 10% Section 5.2 VPP Prog/Erase Voltage 5 V ± 10% or 12 V ± 5%, auto-detected Section 5.2 Bus-width 8- or 16-bit 8- or 16-bit 8- or 16-bit 8-bit Table 2 Speed (ns) Commercial 60, 80 70, 90 60, 80 Section 5.6 Extended 80 80 90 not available Section 5.6 Memory Arrangement x8: 256K x 8 x16: 128K x 16 x8: 512K x 8 x16: 256K x 16 x8: 1M x 8 x16: 512K x 16 x8: 512K x 8 Blocking Boot 1 x 16 KB 1 x 16 KB 1 x 16 KB 1 x 16 KB Section 2.3, Parameter 2 x 8 KB 2 x 8 KB 2 x 8 KB 2 x 8 KB Figs. 4-7 Main 1 x 96 KB 1 x 128 KB 1 x 96 KB 3 x 128 KB 1 x 96 KB 7 x 128 KB 1 x 96 KB 3 x 128 KB Boot Location Top or Bottom boot locations available Locking Boot Block lockable using WP# and/or RP# All other blocks protectable using VPP switch Section 3.3 Operating Temperature Commercial: 0 °C – +70 °C, Extended: -40 °C – +85 °C Section 5.2 Erase Cycling 100,000 cycles at Commercial, 10,000 cycles at Extended Packages 44-PSOP, 48-TSOP 40-TSOP Figs. 1-2 |
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