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changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

November 1995

COPYRIGHT

INTEL CORPORATION 1995

Order Number 290448-005

2-MBIT (128K x 16 256K x 8)

BOOT BLOCK

FLASH MEMORY FAMILY

28F200BX-TB 28F002BX-TB

Y

x8x16 InputOutput Architecture

28F200BX-T 28F200BX-B

For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

x8-only InputOutput Architecture

28F002BX-T 28F002BX-B

For Space Constrained 8-bit

Applications

Y

Upgradeable to Intel’s SmartVoltage

Products

Y

Optimized High-Density Blocked

Architecture

One 16-KB Protected Boot Block

Two 8-KB Parameter Blocks

One 96-KB Main Block

One 128 KB Main Block

Top or Bottom Boot Locations

Y

Extended Cycling Capability

100000 Block Erase Cycles

Y

Automated WordByte Write and

Block Erase

Command User Interface

Status Registers

Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Automatic Power Savings Feature

Static Operation

Y

Hardware Data Protection Feature

EraseWrite Lockout during Power

Transitions

Y

Very High-Performance Read

6080120 ns Maximum Access Time

304040 ns Maximum Output Enable

Time

Y

Low Power Consumption

20 mA Typical Active Read Current

Y

ResetDeep Power-Down Input

Acts as Reset for Boot Operations

Y

Extended Temperature Operation

b

Y

Write Protection for Boot Block

Y

Industry Standard Surface Mount

Packaging

28F200BX JEDEC ROM Compatible

44-Lead PSOP

56-Lead TSOP

28F002BX 40-Lead TSOP

Y

12V WordByte Write and Block Erase

Y

5V Read

Y

Independent Software Vendor Support