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80960CF-25 Datasheet(PDF) 9 Page - Intel Corporation |
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80960CF-25 Datasheet(HTML) 9 Page - Intel Corporation |
9 / 77 page A 80960CF-40, -33, -25, -16 PRELIMINARY 3 The processor also integrates four complete data- chaining DMA channels and a high-speed interrupt controller on-chip. DMA channels perform single- cycle or two-cycle transfers, data packing and unpacking and data chaining. Block transfers — in addition to source or destination synchronized trans- fers — are supported. The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (latency) time of 625 ns. 2.1 The 80960C-Series Core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. This core can sustain execution of two instructions per clock (80 MIPS at 40 MHz). To achieve this level of performance, Intel has incorpo- rated state-of-the-art silicon technology and innova- tive microarchitectural constructs into the C-Series core implementation. Factors that contribute to the core’s performance include: • Parallel instruction decoding allows issuance of up to three instructions per clock • Single-clock execution of most instructions • Parallel instruction decode allows sustained, simultaneous execution of two single-clock instruc- tions every clock cycle • Efficient instruction pipeline minimizes pipeline break losses • Register and resource scoreboarding allow simul- taneous multi-clock instruction execution • Branch look-ahead and prediction allows many branches to execute with no pipeline break • Local Register Cache integrated on-chip caches Call/Return context • Two-way set associative, 4 Kbyte integrated instruction cache • 1 Kbyte integrated Data RAM sustains a four-word (128-bit) access every clock cycle • Direct mapped, 1 Kbyte data cache, write through, write allocate 2.2 Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CF to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at 40 MHz). Inter- nally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Control Unit’s main features include: • Demultiplexed, burst bus to exploit most efficient DRAM access modes • Address pipelining to reduce memory cost while maintaining performance • 32-, 16- and 8-bit modes for I/O interfacing ease • Full internal wait state generation to reduce system cost • Little and Big Endian support to ease application development • Unaligned access support for code portability • Three-deep request queue to decouple the bus from the core 2.3 Instruction Set Summary Table 1 summarizes the 80960CF instruction set by logical groupings. See the i960® Cx Microprocessor User’s Manual (270710) for a complete description of the instruction set. 2.4 Flexible DMA Controller A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disas- sembly and a high performance fly-by mode capable of transfer speeds of up to 71 Mbytes per second at 40 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CF core. |
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