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80960CF-16 Datasheet(PDF) 8 Page - Intel Corporation |
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80960CF-16 Datasheet(HTML) 8 Page - Intel Corporation |
8 / 77 page 2 PRELIMINARY 80960CF-40, -33, -25, -16 A Figure 1. 80960CF Block Diagram Execution Unit Programmable Bus Controller Bus Request Queues Six-Port Register File 64-Bit SRC1 Bus 64-Bit SRC2 Bus 64-Bit DST Bus 32-Bit Base Bus 128-Bit Load Bus 128-Bit Store Bus Instruction Instruction Cache (4 Kbyte, Two-Way Set Associative) 128-BIT CACHE BUS Prefetch Queue Interrupt Controller Control Address Data Memory-side Machine Bus Register-side Machine Bus Parallel Instruction Scheduler Memory Region Configuration Multiply/Divide Unit Four-Channel DMA Controller Interrupt Port 1 Kbyte 5 to 15 Sets Register Cache Data RAM Address Generation Unit F_CF001A DMA Port 1 Kbyte Direct Mapped Data Cache The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions per clock with peak execution of three instructions per clock. A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s high-speed external memory subsystem. Also, the 80960CF’s on-chip caching of instructions, proce- dure context and critical program data substantially decouples system performance from the wait states associated with accesses to the system’s slower, cost sensitive, main memory subsystem. The 80960CF bus controller integrates full wait state and bus width control for highest system perfor- mance with minimal system design complexity. Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CF. |
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