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80960JD-40 Datasheet(PDF) 3 Page - Intel Corporation |
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80960JD-40 Datasheet(HTML) 3 Page - Intel Corporation |
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3 / 61 page  iii PRELIMINARY 80960JD FIGURES Figure 1. 80960JD Microprocessor ...........................................................................................................0 Figure 2. 80960JD Block Diagram ............................................................................................................2 Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13 Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14 Figure 5. 132-Lead PQFP - Top View ..................................................................................................... 17 Figure 6. 50 MHz Maximum Allowable Ambient Temperature ................................................................ 21 Figure 7. 40 MHz Maximum Allowable Ambient Temperature ................................................................ 22 Figure 8. AC Test Load ............................................................................................................................ 33 Figure 9. Output Delay or Hold vs. Load Capacitance ............................................................................ 33 Figure 10. Rise and Fall Time Derating ..................................................................................................... 34 Figure 11. CLKIN Waveform ..................................................................................................................... 34 Figure 12. Output Delay Waveform for T OV1 ............................................................................................. 35 Figure 13. Output Float Waveform for T OF ................................................................................................ 35 Figure 14. Input Setup and Hold Waveform for T IS1 and TIH1 ................................................................... 36 Figure 15. Input Setup and Hold Waveform for T IS2 and TIH2 ................................................................... 36 Figure 16. Input Setup and Hold Waveform for T IS3 and TIH3 ................................................................... 37 Figure 17. Input Setup and Hold Waveform for T IS4 and TIH4 ................................................................... 37 Figure 18. Relative Timings Waveform for T LXL and T LXA ......................................................................... 38 Figure 19. DT/R and DEN Timings Waveform .......................................................................................... 38 Figure 20. TCK Waveform ......................................................................................................................... 39 Figure 21. Input Setup and Hold Waveforms for T BSIS1 and T BSIH1 ......................................................... 39 Figure 22. Output Delay and Output Float Waveform for T BSOV1 and TBSOF1 .......................................... 40 Figure 23. Output Delay and Output Float Waveform for T BSOV2 and TBSOF2 .......................................... 40 Figure 24. Input Setup and Hold Waveform for T BSIS2 and TBSIH2 ........................................................... 41 Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 42 Figure 26. Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43 Figure 27. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 44 Figure 28. Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45 Figure 29. Burst Read and Write Transactions With 1, 0 Wait States and Extra Tr State on Read, 16-Bit Bus ................................................................................... 46 Figure 30. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47 Figure 31. HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48 Figure 32. Cold Reset Waveform .............................................................................................................. 49 Figure 33. Warm Reset Waveform ............................................................................................................ 50 Figure 34. Entering the ONCE State ......................................................................................................... 51 Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54 Figure 36. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 55 |
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Similar Description - 80960JD-40 |
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