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A80960HA33SL2GY Datasheet(PDF) 4 Page - Intel Corporation |
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A80960HA33SL2GY Datasheet(HTML) 4 Page - Intel Corporation |
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4 / 102 page  80960HA/HD/HT iv Advance Information Datasheet Figures 1 80960Hx Block Diagram .......................................................................................1 2 80960Hx 168-Pin PGA Pinout — View from Top (Pins Facing Down) ...............12 3 80960Hx 168-Pin PGA Pinout — View from Bottom (Pins Facing Up) ...............13 4 80960Hx 208-Pin PQ4 Pinout .............................................................................18 5 Measuring 80960Hx PGA Case Temperature ....................................................23 6 80960Hx Device Identification Register ..............................................................26 7 VCC5 Current-Limiting Resistor ..........................................................................30 8 AC Test Load ......................................................................................................37 9 CLKIN Waveform ................................................................................................38 10 Output Delay Waveform ......................................................................................38 11 Output Delay Waveform ......................................................................................38 12 Output Float Waveform .......................................................................................39 13 Input Setup and Hold Waveform .........................................................................39 14 NMI,XINT7:0 Input Setup and Hold Waveform ..................................................39 15 Hold Acknowledge Timings .................................................................................40 16 Bus Backoff (BOFF) Timings ..............................................................................40 17 TCK Waveform....................................................................................................41 18 Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 ....................................41 19 Output Delay and Output Float for TBSOV1 and TBSOF1......................................42 20 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................42 21 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................42 22 Rise and Fall Time Derating at 85°C and Minimum VCC ....................................43 23 ICC Active (Power Supply) vs. Frequency ...........................................................43 24 ICC Active (Thermal) vs. Frequency ....................................................................44 25 Output Delay or Hold vs. Load Capacitance .......................................................44 26 Output Delay vs. Temperature ............................................................................45 27 Output Hold Times vs. Temperature ...................................................................45 28 Output Delay vs. VCC ..........................................................................................45 29 Cold Reset Waveform .........................................................................................46 30 Warm Reset Waveform .......................................................................................47 31 Entering ONCE Mode .........................................................................................48 32 Non-Burst, Non-Pipelined Requests without Wait States ...................................49 33 Non-Burst, Non-Pipelined Read Request with Wait States.................................50 34 Non-Burst, Non-Pipelined Write Request with Wait States .................................51 35 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus .................52 36 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ......................53 37 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54 38 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55 39 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ......................56 40 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ........................57 41 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus .................58 42 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ......................59 43 Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60 44 Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61 45 Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62 46 Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63 47 Using External READY........................................................................................64 48 Terminating a Burst with BTERM ........................................................................65 49 BREQ and BSTALL Operation ............................................................................66 |
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