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TRSL-5120AG Datasheet(PDF) 3 Page - Optoway Technology Inc |
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TRSL-5120AG Datasheet(HTML) 3 Page - Optoway Technology Inc |
3 / 4 page Optoway TRSL-5120G *********************************************************************************************************************************************************************** *********************************************************************************************************************************************************************** OPTOWAY TECHNOLOGY INC. No.38, Kuang Fu S. Road, Hu Kou, Hsin Chu Industrial Park, Hsin Chu, Taiwan 303 Tel: 886-3-5979798 Fax: 886-3-5979737 E-mail: sales@optoway.com.tw http: // www.optoway.com.tw 12/1/2005 V2.0 3 CONNECTION DIAGRAM PIN Symbol Notes 1 VEEr Directly connect this pin to the receiver ground plane 2 VCC r +3.3V dc power for the receiver section 3 SD Active high on this indicates a received optical signal. 4 RD − Receiver Dataout Bar. See recommended circuit schematic 5 RD+ Receiver Dataout. See recommended circuit schematic 6 VCC t +3.3V dc power for the transmitter section 7 VEEt Directly connect this plan to the transmitter ground plane 8 TDis Transmitter Disable. Connect this pin to +3.3V TTL logic “1” to disable module To enable module connect to TTL logic low “0” 9 TD+ Transmitter Data In. See recommended circuit schematic 10 TD- Transmitter Data In Bar. See recommended circuit schematic MS MS Mounting Studs. Connect to Chassis Ground RECOMMENDED CIRCUIT SCHEMATIC SFF2X5 TDis(LVTTL) 1uH 10uF 10nF 10uF 10nF Vcc3.3V 1uH 10uF 10nF 1K PHY DEVICE TD- TD+ RD+ RD- SD 130R 82R Vcc3.3V 130R 82R Vcc3.3V Vcc3.3V LVPECL Vcc3.3V LVPECL TO LVPECL STAGE 150ohm 150ohm MICROSTRIP2 Z=5OR MICROSTRIP1 Z=50R MICROSTRIP4 Z=5OR MICROSTRIP3 Z=50R Note: 1. 1000ΩSD Output pull-down resistor required for TRSL-5120G / TRSL-5120AG (LVPECL SD Output) 2. No pull-down resistor required for TRSL-5120CG / TRSL-5120ACG (LVTTL SD Output) 3. Veer and Veet are not internally connected to each other. 4. 50 Ω line pattern and component placements on TD+/TD- and RD+/RD- lines shall be symmetrical for better impedance matching. |
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