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82093AA Datasheet(PDF) 9 Page - Intel Corporation |
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82093AA Datasheet(HTML) 9 Page - Intel Corporation |
9 / 20 page 82093AA (IOAPIC) 9 PRELIMINARY 3.1. Memory Mapped Registers for Accessing IOAPIC Registers 3.1.1. IOREGSEL—I/O REGISTER SELECT REGISTER Memory Address: FEC0 xy00h (xy=See APICBASE Register in the PIIX3) Default Value: 00h Attribute: Read/Write This register selects the IOAPIC Register to be read/written. The data is then read from or written to the selected register through the IOWIN Register. Bit Description 31:8 Reserved. 7:0 APIC Register Address—R/W. Bits [7:0] specify the IOAPIC register to be read/written via the IOWIN Register. 3.1.2. IOWIN—I/O WINDOW REGISTER Memory Address: FEC0 xy10h (xy=See APICBASE Register in PIIX3) Default Value: 00h Attribute: Read/Write This register is used to write to and read from the register selected by the IOREGSEL Register. Readability/writability is determined by the IOAPIC register that is currently selected. Bit Description 31:0 APIC Register Data—R/W. Memory references to this register are mapped to the APIC register specified by the contents of the IOREGSEL Register. 3.2. IOAPIC Registers 3.2.1. IOAPICID—IOAPIC IDENTIFICATION REGISTER Address Offset: 00h Default Value: 00h Attribute: Read/Write This register contains the 4-bit APIC ID. The ID serves as a physical name of the IOAPIC. All APIC devices using the APIC bus should have a unique APIC ID. The APIC bus arbitration ID for the I/O unit is also writtten during a write to the APICID Register (same data is loaded into both). This register must be programmed with the correct ID value before using the IOAPIC for message transmission. Bit Description 31:28 Reserved. 27:24 IOAPIC Identification—R/W. This 4 bit field contains the IOAPIC identification. 23:0 Reserved. |
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Similar Description - 82093AA |
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