82093AA (IOAPIC)

5

PRELIMINARY

2.0.

SIGNAL DESCRIPTION

This section contains a detailed description of each signal. The signals are arranged in function groups

according to their interface.

Note that the “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the

signal is at a low voltage level. When “#” is not present after the signal name, the signal is asserted when at the

high voltage level.

The terms' assertion and negation are used extensively. This is done to avoid confusion when working with a

mixture of ‘active-low’ and ‘active-high’ signals. The term assert, or assertion indicates that a signal is active,

independent of whether that level is represented by a high or low voltage. The term negate, or negation indicates

that a signal is inactive.

The following notations are used to describe the signal and type:

I

Input pin

O

Output pin

ST

Schmitt Trigger Input pin

OD

Open Drain Output pin. This requires a pull-up to the VCC of the processor core

I/OD

Bi-directional Input withOpen Drain Output pin.

I/O

Bi-directional Input/Output pin

2.1.

System Bus Signals

Signal Name

Type

Description

D[7:0]

I/O

DATA: D[7:0] contain the data when writing to or reading from internal IOAPIC

registers. These signals are outputs when reading data from the IOAPIC and

they are inputs when writing data to the IOAPIC. These signals are tri-stated

during reset.

D/I#

I

DATA/INDEX#: This input selects whether the I/O Register Select

(IOREGSEL) Register or I/O Window (IOWIN) Register is accessed. All

internal IOAPIC registers are accessed with an indexing scheme. When the

D/I# pin is low, the IOREGSEL Register is accessed. When the D/I# pin is

high, the data becomes available from the register pointed to by the index

register. Typically, this signal is connected to SA4 on the ISA bus (i.e.,

IOREGSEL Register is at 00h and IOWIN Register is at 10h).

A[1:0]

I

ADDRESS: The IOAPIC is a 32 bit device with an 8 bit ISA interface. A[1:0]

steer the data byte to the correct 8 bit location within the 32 bit register.

Typically, these input signals are connected to SA[1:0] of the ISA bus.

RD#

I

READ STROBE: RD# causes the IOAPIC to respond by driving internal

register data onto the D[7:0] pins. Typically this pin is connected to the

MEMRD# signal on the ISA bus.

WR#

I

WRITE STROBE: When this signal transitions from low to high, the data

present on the IOAPIC’s D[7:0] signals are written to an internal register.

Typically, this signal is connected to the MEMWR# signal on the ISA bus.

CS#

I

CHIP SELECT: This active low input selects the IOAPIC as the target of the

current read or write transaction.