KU80L186EC13 datasheet(9/57 Pages) INTEL

Part #	KU80L186EC13

Description	16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS

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Manufacturer	INTEL [Intel Corporation]

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80C186EC188EC 80L186EC188EC

Column 4 Output States (for O and IO types

only)

The state of an output or IO pin is de-

pendent on the operating mode of the

device There are four modes of opera-

tion that are different from normal active

mode Bus Hold Reset Idle Mode Pow-

erdown Mode This column describes

the output pin state in each of these

modes

The legend for interpreting the information in the Pin

Descriptions is shown in Table 1

As an example please refer to the table entry for

AD120 The ‘‘IO’’ signifies that the pins are bidirec-

tional (ie have both an input and output function)

The ‘‘S’’ indicates that as an input the signal must

be synchronized to CLKOUT for proper operation

The ‘‘H(Z)’’ indicates that these pins will float while

the processor is in the Hold Acknowledge state

R(Z) indicates that these pins will float while RESIN

is low P(0) and I(0) indicate that these pins will drive

0 when the device is in either Powerdown or Idle

Mode

Some pins the IO Ports for example can be pro-

grammed to perform more than one function Multi-

function pins have a ‘‘’’ in their signal name be-

tween the different functions (ie P30RXI1) If the

input pin type or output pin state differ between func-

tions then that will be indicated by separating the

state (or type) with a ‘‘’’ (ie H(X)H(Q)) In this

example when the pin is configured as P30 then its

hold output state is H(X) when configured as RXI1

its output state is H(Q)

All pins float while the processor is in the ONCE

Mode (with the exception of OSCOUT)

Table 1 Pin Description Nomenclature

Symbol

Description

P

Power Pin (apply a VCC voltage)

G

Ground (connect to VSS)

I

Input only pin

O

Output only pin

IO

InputOutput pin

S(E)

Synchronous edge sensitive

S(L)

Synchronous level sensitive

A(E)

Asynchronous edge sensitive

A(L)

Asynchronous level sensitive

H(1)

Output driven to VCC during bus hold

H(0)

Output driven to VSS during bus hold

H(Z)

Output floats during bus hold

H(Q)

Output remains active during bus hold

H(X)

Output retains current state during bus hold

R(WH)

Output weakly held at VCC during reset

R(1)

Output driven to VCC during reset

R(0)

Output driven to VSS during reset

R(Z)

Output floats during reset

R(Q)

Output remains active during reset

R(X)

Output retains current state during reset

I(1)

Output driven to VCC during Idle Mode

I(0)

Output driven to VSS during Idle Mode

I(Z)

Output floats during Idle Mode

I(Q)

Output remains active during Idle Mode

I(X)

Output retains current state during Idle Mode

P(1)

Output driven to VCC during Powerdown Mode

P(0)

Output driven to VSS during Powerdown Mode

P(Z)

Output floats during Powerdown Mode

P(Q)

Output remains active during Powerdown Mode

P(X)

Output retains current state during Powerdown Mode

9

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