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TS80C188EB20 Datasheet(PDF) 5 Page - Intel Corporation |
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TS80C188EB20 Datasheet(HTML) 5 Page - Intel Corporation |
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5 / 59 page  80C186EB80C188EB 80L186EB80L188EB 272433 – 3 (A) Crystal Connection NOTE The L1C1 network is only required when using a third- overtone crystal 272433 – 4 (B) Clock Connection Figure 2 Clock Configurations The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Resistance) 40X max C0 (Shunt Capacitance of Crystal) 70 pF max CL (Load Capacitance) 20 pF g 2pF Drive Level 1 mW max 80C186EB PERIPHERAL ARCHITECTURE The 80C186EB has integrated several common sys- tem peripherals with a CPU core to create a com- pact yet powerful system The integrated peripher- als are designed to be flexible and provide logical interconnections between supporting units (eg the interrupt control unit supports interrupt requests from the timercounters or serial channels) The list of integrated peripherals includes 7-Input Interrupt Control Unit 3-Channel TimerCounter Unit 2-Channel Serial Communications Unit 10-Output Chip-Select Unit IO Port Unit Refresh Control Unit Power Management Unit The registers associated with each integrated peri- heral are contained within a 128 x 16 register file called the Peripheral Control Block (PCB) The PCB can be located in either memory or IO space on any 256 Byte address boundary Figure 3 provides a list of the registers associated with the PCB The Register Bit Summary at the end of this specification individually lists all of the regis- ters and identifies each of their programming attri- butes Interrupt Control Unit The 80C186EB can receive interrupts from a num- ber of sources both internal and external The inter- rupt control unit serves to merge these requests on a priority basis for individual service by the CPU Each interrupt source can be independently masked by the Interrupt Control Unit (ICU) or all interrupts can be globally masked by the CPU Internal interrupt sources include the Timers and Se- rial channel 0 External interrupt sources come from the five input pins INT40 The NMI interrupt pin is not controlled by the ICU and is passed directly to the CPU Although the Timer and Serial channel each have only one request input to the ICU sepa- rate vector types are generated to service individual interrupts within the Timer and Serial channel units TimerCounter Unit The 80C186EB TimerCounter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repeti- tive waveforms generate timed interrupts etc 5 5 |
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