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IDT74FCT825BTEB Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT74FCT825BTEB Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 9 page IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.21 3 FUNCTION TABLE (1) PIN DESCRIPTION 2567 tbl 01 ABSOLUTE MAXIMUM RATINGS (1) CAPACITANCE (TA = +25 °C, f = 1.0MHz) Symbol Rating Commercial Military Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to +7.0 –0.5 to +7.0 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC +0.5 –0.5 to VCC +0.5 V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 0.5 0.5 W IOUT DC Output Current –60 to +120 –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. NOTE: 1. This parameter is measured at characterization but not tested. 2567 lnk 03 2567 lnk 04 Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF Inputs Internal/ Outputs OE OE CLR CLR EN EN DI CP QI YI Function H H H H L L L H ↑ ↑ L H Z Z High Z H L L L X X X X X X L L Z L Clear H L H H H H X X X X NC NC Z NC Hold H H L L H H H H L L L L L H L H ↑ ↑ ↑ ↑ L H L H Z Z L H Load Names I/O Description DI I The D flip-flop data inputs. CLR I When the clear input is LOW and OE is LOW, the QI outputs are LOW. When the clear input is HIGH, data can be entered into the register. CP I Clock Pulse for the Register; enters data into the register on the LOW-to- HIGH transition. YI O The register 3-state outputs. EN I Clock Enable. When the clock enable is LOW, data on the D I input is transferred to the QI output on the LOW-to-HIGH clock transition. When the clock enable is HIGH, the QI outputs do not change state, regardless of the data or clock input transitions. OE I Output Control. When the OE input is HIGH, the Y I outputs are in the high- impedance state. When the OE input is LOW, the TRUE register data is present at the YI outputs. NOTE: 2567 tbl 02 1. H = HIGH L = LOW X = Don’t Care NC = No Change ↑ = LOW-to-HIGH Transition Z = High Impedance |
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