IDT54FCT821ALB datasheet(7/8 Pages) IDT

Part #	IDT54FCT821ALB

Description	HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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Manufacturer	IDT [Integrated Device Technology]

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IDT54/74FCT821/823/824/825A/B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.19

7

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

ENABLE AND DISABLE TIMES

PROPAGATION DELAY

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

Pulse

Generator

DATA

INPUT

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

ETC.

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

t SU

t H

t REM

H

t SU

R T

D.U.T.

VCC

VIN

C L

V OUT

50pF

500

Ω

500

Ω

7.0V

SAME PHASE

INPUT TRANSITION

3V

1.5V

0V

1.5V

VOH

VOL

tPLH

t PHL

OUTPUT

OPPOSITE PHASE

INPUT TRANSITION

CONTROL

INPUT

3V

1.5V

0V

3.5V

0V

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

SWITCH

CLOSED

SWITCH

OPEN

V OL

V OH

3V

1.5V

0V

t PLH

tPHL

0.3V

tPLZ

tPZL

tPZH

tPHZ

3.5V

0V

1.5V

ENABLE

DISABLE

HIGH-LOW-HIGH

PULSE

LOW-HIGH-LOW

PULSE

t W

1.5V

t

NOTES

2608 drw 01

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

2. Pulse Generator for All Pulses: Rate

≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;

tR

≤ 2.5ns.

SWITCH POSITION

Test

Switch

Open Drain

Disable Low

Closed

Enable Low

All Other Tests

Open

DEFINITIONS:

2608 tbl 09

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

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