IDT74FCT821ALB datasheet(3/8 Pages) IDT

Part #	IDT74FCT821ALB

Description	HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

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Manufacturer	IDT [Integrated Device Technology]

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IDT54/74FCT821/823/824/825A/B/C

HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

7.19

3

PRODUCT SELECTOR GUIDE

2608 tbl 01

PIN DESCRIPTION

FUNCTION TABLE

(1)

IDT54/74FCT821/823/825

FUNCTION TABLE

(1)

IDT54/74FCT824

2608 tbl 10

Device

10-Bit

9-Bit

8-Bit

Non-inverting

54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C

Inverting

54/74FCT824A/B/C

NOTE:

2608 tbl 02

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,

↑ = LOW-to-HIGH

Transition, Z = High Impedance

NOTE:

2608 tbl 03

1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change,

↑ = LOW-to-

HIGH Transition, Z = High Impedance

Name

I/O

Description

DI

I

The D flip-flop data inputs.

CLR

I

For both inverting and non-inverting

registers, when the clear input is LOW

and

OE is LOW, the QI outputs are

LOW. When the clear input is HIGH,

data can be entered into the register.

CP

I

Clock Pulse for the Register; enters

data into the register on the LOW-to-

HIGH transition.

YI , YI

O

The register three-state outputs.

EN

I

Clock Enable. When the clock enable

is LOW, data on the D I input

is

transferred to the QI output on the

LOW-to-HIGH clock transition. When

the clock enable is HIGH, the QI

outputs

do

not

change

state,

regardless of the data or clock input

transitions.

OE

I

Output Control. When the

OE input is

HIGH, the Y I outputs are in the high

impedance state. When the

OE input is

LOW,

the

TRUE

register

data

is

present at the Y I outputs.

Inputs

Internal/

Outputs

OE

CLR

EN

DI

CP

QI

YI

Function

H

L

H

↑

L

H

Z

High Z

H

L

X

L

Z

L

Clear

H

L

H

X

NC

Z

NC

Hold

H

L

H

L

H

L

H

↑

L

H

L

H

Z

L

H

Load

Inputs

Internal/

Outputs

OE

CLR

EN

DI

CP

QI

YI

Function

H

L

H

↑

H

L

Z

High Z

H

L

X

L

Z

L

Clear

H

L

H

X

NC

Z

NC

Hold

H

L

H

L

H

L

H

↑

H

L

H

L

Z

H

L

Load

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