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M87C51FC-1 Datasheet(PDF) 5 Page - Intel Corporation

Part # M87C51FC-1
Description  CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 32 KBYTES USER PROGRAMMABLE EPROM
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

M87C51FC-1 Datasheet(HTML) 5 Page - Intel Corporation

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M87C51FC
271114 – 5
Figure 4 External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode When
the microcontroller is in this mode power consump-
tion is reduced The Special Function Registers and
the onboard RAM retain their values during Idle but
the processor stops executing instructions
Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs The PCA timercounter can
optionally be left running or paused during Idle
Mode
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the M87C51FC either a hardware reset or an
external interrupt can cause an exit from Power
Down Reset redefines all the SFRs but does not
change the on-chip RAM An external interrupt al-
lows both the SFRs and on-chip RAM to retain their
values
To properly terminate Power down the reset or ex-
ternal interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
DESIGN CONSIDERATION
 The window on the M87C51FC must be covered
by an opaque label Otherwise the DC and AC
characteristics may not be met and the device
may functionally be impaired
 When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing
and
debugging
of
systems
using
the
M87C51FC without the M87C51FC having to be re-
moved from the circuit The ONCE Mode is invoked
by
1) Pull ALE low while the device is in reset and
PSEN is high
2) Hold ALE low as RST is deactivated
While the device is in ONCE Mode the Port 0 pins
go into a float state and the other port pins and ALE
and PSEN are weakly pulled high The oscillator cir-
cuit remains active While the M87C51FC is in this
mode an emulator or test CPU can be used to drive
the circuit Normal operation is restored when a nor-
mal reset is applied
Table 1 Status of the External Pins during Idle and Power Down
Mode
Program
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Memory
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE
For more detailed information on the reduced power modes refer to Application Note AP-255 ‘‘Military CHMOS Designing
with the M80C51BH’’
5


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