8

t6

Status Hold Time

1

-

1

-

ns

t7

F/C Setup Time

15

-

15

-

t8

F/C Hold Time

15

-

15

-

t9

SRDY or SRDYEN Setup Time

15

-

15

-

ns

t10

SRDY or SRDYEN Hold Time

2

-

2

-

ns

t11

ARDY or ARDYEN Setup Time

5

-

5

-

ns

(Note 3)

t12

ARDY or ARDYEN Hold Time

30

-

25

-

ns

(Note 3)

t13

RES Setup Time

20

-

18

-

ns

(Notes 3, 7)

t14

RES Hold Time

10

-

8

-

ns

(Notes 3, 7)

t16

CLK Period

50

-

40

-

t17

CLK LOW Time

12

-

11

-

ns

(Notes 2, 6)

t18

CLK HIGH Time

16

-

13

-

ns

(Notes 2, 6)

t21

READY Inactive Delay

5

-

5

-

ns

At 0.8V (Note 4), Test Condition 2

t22

READY Active Delay

-

24

-

18

ns

At 0.8V (Note 4)

t23

PCLK Delay

-

20

-

16

ns

t24

RESET Delay

-

27

-

26

ns

t25

PCLK LOW Time

t16 -10

-

t16 -10

-

na

t26

PCLK HIGH Time

t16 -10

-

t16 -10

-

ns

NOTES:

ground; for CLK frequencies from 20MHz to 25MHz the recommended loading is 15pF from pin X1 to GND. These recommended values

3. This is an asynchronous input. This specification is given for testing purposes only, to assure recognition at a specific CLK edge.

4. The pull-up resistor value for the READY pin is 620

Ω with the rated 150pF load.

6. When using a crystal with the recommended capacitive loading, CLK output HIGH and LOW times are guaranteed to meet 80C286 re-

quirements.

7. Measured from 1.0V on the CLK to 0.8V on the RES waveform for RES waveform for RES active and to 4.2V on the RES waveform for

RES inactive.

AC Electrical Specifications

AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Waveforms,

Unless Otherwise Noted.

SYMBOL

PARAMETER

10MHz

12.5MHz

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNTESTED SPECIFICATIONS

SYMBOL

PARAMETER

10MHz

12.5MHz

UNITS

CONDlTIONS (NOTE 1)

MIN

MAX

MIN

MAX

Input Capacitance

-

10

-

10

pF

FREQ = 1MHz, All measurements are

t15A

EFI HIGH to CLK LOW Delay

-

30

-

25

ns

(Note 2)

t15B

EFI LOW to CLK HIGH Delay

-

35

-

30

ns

(Note 3)

82C284