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MG80C883-10 Datasheet(PDF) 11 Page - Intersil Corporation

Part # MG80C883-10
Description  High Performance Microprocessor with Memory Management and Protection
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

MG80C883-10 Datasheet(HTML) 11 Page - Intersil Corporation

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3-138
80C286/883
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in
φ2 of T
C.
3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to ex-
ternal HOLD. The float starts in
φ1 of T
C.
4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
Waveforms (Continued)
VALID
VALID
VALID
(SEE NOTE 3)
(SEE NOTE 2)
(SEE NOTE 1)
(SEE NOTE 6)
(SEE NOTE 5)
NOT READY NOT READY
NOT READY NOT READY
(SEE NOTE 7)
READY
(SEE NOTE 7)
DELAY ENABLE
VOH
TH
φ2
φ1
TH
φ2
φ1
TH
φ2
φ1
BUS HOLD ACKNOWLEDGE
TS
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TC
φ2
φ1
TI
φ2
φ1
TH
φ2
φ1
BUS HOLD
ACKNOWLEDGE
WRITE CYCLE
BUS CYCLE TYPE
CLK
HOLD
(SEE NOTE 4)
HLDA
S1
• S0
A23 - A0
M/IO,
D15 - D0
SRDY +
ARDY +
CMDLY
MWTC
DT/R
ALE
COD/INTA
BHE, LOCK
SRDYEN
ARDYEN
DEN
TS - STATUS CYCLE
CT - COMMAND CYCLE
(SEE NOTE 1)


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