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CG80C286-12 Datasheet(PDF) 9 Page - Intersil Corporation |
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CG80C286-12 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 13 page 3-136 80C286/883 NOTES: 1. PCLK indicates which processor cycle phase will occur on the next CLK. PCLK may not indicate the correct phase until the first cycle is performed. 2. These inputs are asynchronous. The setup and hold times shown assure recognition for testing purposes. FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL TIMING NOTE: 1. When RESET meets the setup time shown, the next CLK will start or repeat φ1 of a processor cycle. FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE- QUENT PROCESSOR CYCLE PHASE NOTES: 1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown. 2. The data bus will be driven as shown if the last cycle before TI in the diagram was a write TC. 3. The 80C286/883 puts its status pins in a high impedance logic one state during TH. 4. For HOLD request set up to HLDA, refer to Figure 8. 5. BHE and LOCK are driven at this time but will not become valid until TS. 6. The data bus will remain in a high impedance state if a read cycle is performed. FIGURE 5. EXITING AND ENTERING HOLD Waveforms (Continued) φ2 BUS CYCLE TYPE VCH VCL CLK φ1 PCLK (SEE NOTE 1) TX INTR, NMI HOLD, PEREQ (SEE NOTE 2) ERROR, BUSY (SEE NOTE 2) 19 19 4 5 5 4 φ2 7 RESET φ1 φ1 φ2 6 VCH VCL CLK (SEE NOTE 1) TX VCH CLK VCL RESET TX φ2 φ2 φ1 7 6 (SEE NOTE 1) 16 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 TH TI TH TH OR TI BUS CYCLE TYPE VCH CLK HILDA VCL 16 (SEE NOTE 4) 12A (NOTE 3) 15 (SEE NOTE 3) 12B 15 IF TS S1 • S0 PEACK BHE, LOCK A23 - A0, M/IO, COD/INTA (SEE NOTE 5) 13 (SEE NOTE 1) 15 VALID 14 (SEE NOTE 6) (SEE NOTE 2) 15 VALID IF WRITE D15 - D0 PCLK IF NPX TRANSFER |
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