3-136

80C286/883

NOTES:

1. PCLK indicates which processor cycle phase will occur on the

next CLK. PCLK may not indicate the correct phase until the first

cycle is performed.

2. These inputs are asynchronous. The setup and hold times shown

assure recognition for testing purposes.

FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL

TIMING

NOTE:

1. When RESET meets the setup time shown, the next CLK will

start or repeat

φ1 of a processor cycle.

FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-

QUENT PROCESSOR CYCLE PHASE

NOTES:

1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.

4. For HOLD request set up to HLDA, refer to Figure 8.

6. The data bus will remain in a high impedance state if a read cycle is performed.

FIGURE 5. EXITING AND ENTERING HOLD

φ2

BUS CYCLE TYPE

CLK

φ1

PCLK

(SEE NOTE 1)

INTR, NMI

HOLD, PEREQ

(SEE NOTE 2)

ERROR, BUSY

(SEE NOTE 2)

19

19

4

5

5

4

φ2

7

RESET

φ1

φ1

φ2

6

CLK

(SEE NOTE 1)

CLK

RESET

φ2

φ2

φ1

7

6

(SEE NOTE 1)

16

φ2

φ1

φ2

φ1

φ2

φ1

φ2

φ1

BUS CYCLE TYPE

CLK

HILDA

16

(SEE NOTE 4)

12A (NOTE 3)

15

(SEE NOTE 3)

12B

15

S1 • S0

PEACK

BHE, LOCK

M/IO,

COD/INTA

(SEE NOTE 5)

13

(SEE NOTE 1)

15

VALID

14

(SEE NOTE 6)

(SEE NOTE 2)

15

VALID IF WRITE

PCLK

IF NPX TRANSFER