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IS82C50A-5 Datasheet(PDF) 9 Page - Intersil Corporation |
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IS82C50A-5 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 21 page 9 Serial Output (SOUT) is set to the marking (logic 1) state, and the receiver data input Serial Input (SIN) is discon- nected. The output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. The four modem control inputs (CTS, DSR, DC, and RI) are disconnected. The four modem control outputs (DTR, RTS, OUT1 and OUT2) are internally connected to the four modem control inputs. The modem control output pins are forced to their inactive state (high). In the diagnostic mode, data transmitted is immediately received. This allows the proces- sor to verify the transmit and receive data paths of the 82C50A. In the diagnostic mode, the receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the MCR instead of the four modem control inputs. The interrupts are still controlled by the Interrupt Enable Register. MCR(5) - MCR(7): These bits are permanently set to logic 0. MODEM STATUS REGISTER (MSR) The MSR provides the CPU with status of the modem input lines from the modem or peripheral device. The MSR allows the CPU to read the modem signal inputs by accessing the data bus interface of the 82C50A. In addition to the current status information, four bits of the MSR indicate whether the modem inputs have changed since the last reading of the MSR. The delta status bits are set high when a control input from the modem changes state, and reset low when the CPU reads the MSR. The modem input lines are CTS (pin 36), DSR (pin 37), RI (pin 39), and DCD (pin 38). MSR(4) - MSR(7) are status indi- cations of these lines. The status indications follow the sta- tus of the input lines. If the modem status interrupt in the Interrupt Enable Register is enabled (IER(3)), a change of state in a modem input signals will be reflected by the modem status bits in the lIR register, and an interrupt (lNTRPT) is generated. The MSR is a priority 4 interrupt. The contents of the Modem Status Register are described below: Note that the state (high or low) of the status bits are inverted versions of the actual input pins. MSR(0) Delta Clear to Send (DCTS): DCTS indicates that the CTS input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(1) Delta Data Set Ready (DDSR): DDSR indicates that the DSR input (Pin-37) to the 62C50A has changed state since the last time it was read by the CPU. MSR(2) Trailing Edge of Ring Indicator (TERI): TERI indi- cates that the RI input (Pin-39) to the 82C50A has Changed state from Low to High since the last time it was read by the CPU. High to Low transitions on RI do not activate TERI. MSR(3) Delta Data Carrier Detect (DDCD): DDCD indi- cates that the DCD input (Pin-36) to the 82C50A has changed state since the last time it was read by the CPU. MSR(4) Clear to Send (CTS): Clear to Send (CTS) is the status of the CTS input (Pin-36) from the modem indicating to the 82C50A that the modem is ready to receive data from the 62C50A transmitter output (SOUT). If the 82C50A is in Modem Control Register (MCR) MCR 7 MCR 6 MCR 5 MCR 4 MCR 3 MCR 2 MCR 1 MCR 0 Data Terminal Ready 0 = DTR Output High (Inactive) 1 = DTR Output Low (Active) Request to Send 0 = RTS Output High (Inactive) 1 = RTS Output Low (Active) Out 1 0 = OUT 1 Output High (Inactive) 1 = OUT 1 Output Low (Active) Out 2 0 = OUT 2 Output High (Inactive) 1 = OUT 2 Output Low (Active) Loop 0 = Loop Disabled 1 = Loop Enabled These Bits are Permanently Set to a Logic 0. MSR BITS 0 THRU 7 MSR BIT MNEMONIC DESCRIPTION MSR (1) DDSR Delta Data Set Ready MSR (2) TERI Trailing Edge of Ring Indicator MSR (0) DCTS Delta Clear To Send MSR (3) DDCD Delta Data Carrier Detect MSR (4) CTS Clear To Send MSR (5) DSR Data Set Ready MSR (6) RI Ring Indicator MSR (7) DCD Data Carrier Detect 82C50A |
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