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ID82C37A-5 Datasheet(PDF) 7 Page - Intersil Corporation |
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ID82C37A-5 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 23 page 4-198 82C37A the initial 82C37A.This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since the cascade channel of the initial 82C37A is used only for prioritizing the additional device, it does not output an address or control signals of its own. These could conflict with the outputs of the active chan- nel in the added device. The initial 82C37A will respond to DREQ and generate DACK but all other outputs except HRQ will be disabled. An external EOP will be ignored by the initial device, but will have the usual effect on the added device. Figure 3 shows two additional devices cascaded with an initial device using two of the initial device’s channels. This forms a two-level DMA system. More 82C37As could be added at the second level by using the remaining channels of the first level. Additional devices can also be added by cascading into the channels of the second level devices, forming a third level. When programming cascaded controllers, start with the first level device (closest to the microprocessor). After RESET, the DACK outputs are programmed to be active low and are held in the high state. If they are used to drive HLDA directly, the second level device(s) cannot be programmed until DACK polarity is selected as active high on the initial device. Also, the initial device’s mask bits function normally on cascaded channels, so they may be used to inhibit second- level services. Transfer Types Each of the three active transfer modes can perform three dif- ferent types of transfers. These are Read, Write and Verify. Write transfers move data from an I/O device to the memory by activating MEMW and IOR. Read transfers move data from memory to an I/O device by activating MEMR and IOW. Verify transfers are pseudo-transfers. The 82C37A operates as in Read or Write transfers generating addresses and responding to EOP, etc., however the memory and I/O control lines all remain inactive. Verify mode is not permitted for memory-to-memory operation. READY is ignored during Verify transfers. Autoinitialize - By setting bit 4 in the Mode register, a channel may be set up as an Autoinitialize channel. During Autoinitialization, the original values of the Current Address and Current Word Count registers are automatically restored from the Base Address and Base Word Count registers of the channel following EOP. The base registers are loaded simultaneously with the current registers by the micropro- cessor and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in Autoinitialize mode. Following Autoinitialization, the channel is ready to perform another DMA service, without CPU intervention, as soon as a valid DREQ is detected, or software request made. Memory-to-Memory - To perform block moves of data from one memory address space to another with minimum of program effort and time, the 82C37A includes a memory-to- memory transfer feature. Setting bit 0 in the Command register selects channels 0 and 1 to operate as memory-to- memory transfer channels. The transfer is initiated by setting the software or hardware DREQ for channel 0. The 82C37A requests a DMA service in the normal manner. After HLDA is true, the device, using four-state transfers in Block Transfer mode, reads data from the memory. The channel 0 Current Address register is the source for the address used and is decremented or incremented in the normal manner. The data byte read from the memory is stored in the 82C37A internal Temporary reg- ister. Another four-state transfer moves the data to memory using the address in channel one’s Current Address register and incrementing or decrementing it in the normal manner. The channel 1 Current Word Count is decremented. When the word count of channel 1 decrements to FFFFH, a TC is generated causing an EOP output, terminating the service, and setting the channel 1 TC bit in the Status register. The channel 1 mask bit will also be set, unless the channel 1 mode register is programmed for autoinitialization. Channel 0 word count decrementing to FFFFH will not set the channel 0 TC bit in the status register nor generate an EOP, nor set the channel 0 mask bit in this mode. It will cause an autoinitialization of channel 0, if that option has been selected. If full Autoinitialization for a memory-to-memory operation is desired, the channel 0 and channel 1 word counts must be set to equal values before the transfer begins. Otherwise, if channel 0 underflows before channel 1, it will autoinitialize and set the data source address back to the beginning of the block. If the channel 1 word count underflows before channel 0, the memory-to-memory DMA service will terminate, and channel 1 will autoinitialize but channel 0 will not. In memory-to-memory mode, Channel 0 may be programmed to retain the same address for all transfers. This allows a single byte to be written to a block of memory. This channel 0 address hold feature is selected by setting bit 1 in the Command register. The 82C37A will respond to external EOP signals during memory-to-memory transfers, but will only relinquish the system busses after the transfer is complete (i.e. after an 80C86/88 MICRO- PROCESSOR HRQ HLDA DREQ DACK DREQ DACK 1ST LEVEL 82C37A HRQ HLDA 82C37A HRQ HLDA 82C37A ADDITIONAL DEVICES 2ND LEVEL INITIAL DEVICE FIGURE 3. CASCADED 82C37As |
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