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82C50 Datasheet(PDF) 6 Page - Intersil Corporation |
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82C50 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 21 page  6 Accessible Registers The three types of internal registers in the 82C50A used in the operation of the device are control, status, and data registers. The control registers are the Bit Rate Select Register DLL and DLM, Line Control Register, Interrupt Enable Register and the Modem Control registers, while the status registers are the Line Status Registers and the Modem Status Register. The data registers are the Receiver Buffer Register and Transmitter Holding Register. The Address, Read, and Write inputs are used in conjunction with the Divisor Latch Access Bit in the Line Control Register (LCR(7)) to select the register to be written or read (see Table 1.). Individual bits within these registers are referred to by the register mnemonic and the bit number in parenthesis. An example, LCR(7) refers to Line Control Register Bit 7. The Transmitter Buffer Register and Receiver Buffer Regis- ter are data registers holding from 5-8 data bits. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The 82C50A data registers are double buffered so that read and write operations can be performed at the same time the UART is performing the par- allel to serial and serial to parallel conversion. This provides the microprocessor with increased flexibility in its read and write timing. TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS DLAB A2 A1 A0 MNEMONIC REGISTER 0 0 0 0 RBR Receiver Buffer Register (read only) 0 0 0 0 THR Transmitter Holding Register (write only) 0 0 0 1 lER Interrupt Enable Register X 0 1 0 IIR Interrupt Identifica- tion Register (read only) X 0 1 1 LCR Line Control Register X 1 0 0 MCR Modem Control Register X 1 0 1 LSR Line Status Register X 1 1 0 MSR Modem Status Register X 1 1 1 SCR Scratch Register 1 0 0 0 DLL Divisor Latch (LSB) 1 0 0 1 DLM Divisor Latch (MSB) NOTE: X = “Don’t Care”, 0 = Logic Low, 1 = Logic High Line Control Register (LCR) LCR 7 LCR 6 LCR 5 LCR 4 LCR 3 LCR 2 LCR 1 LCR 0 Word Length Select 0 0 = 5 Data Bits 0 1 = 6 Data Bits 1 0 = 7 Data Bits 1 1 = 8 Data Bits Stop Bit Select 0 = 1 Stop Bit 1 = 1.5 Stop Bits if 5 Data Bit Word Length is Selected 2 Stop Bits if 6, 7, or 8 Data Bit Word Length is Selected Parity Enable 0 = Parity Disabled 1 = Parity Enabled (Generated & Checked) Even Parity Select 0 = Odd Parity When Parity is Enabled 1 = Even Parity When Parity is Enabled Stick Parity 0 = Stick Parity Disabled 1 = When Parity is Enabled Forces the Transmission and Checking of a Parity Bit of a Known State. Parity Bit Forced to a Logic 1 if LCR (4) = 0 or to a Logic 0 If LCR (4) = 1. Break Control 0 = Break Disabled 1 = Break Enabled. The Serial Output (SOUT) is Forced to the Spacing (Logic 0) State. Divisor Latch Access Bit 0 = Must be Low to Access the Receiver Buffer. Transmitter Holding Register or the Interrupt Enable Register. 1 = Must be High to Access the Divisor Latches DLL and DLM of the Baud Rate Generator During a Read or Write Operation. 82C50A |
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