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CD82C88 Datasheet(PDF) 6 Page - Intersil Corporation

Part # CD82C88
Description  CMOS Bus Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

CD82C88 Datasheet(HTML) 6 Page - Intersil Corporation

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AC Testing Input, Output Waveform
A.C. Testing: All input signals (other than CLK) must switch
between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V
and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
AC Electrical Specifications VCC = 5.0V ± 10%;
TA = 0
oC to +70oC (C82C88);
TA = -40
oC to +85oC (I82C88);
TA = -55
oC to +125oC (M82C88)
SYMBOL
PARAMETER
8MHz
10MHz
12MHz
UNITS
TEST
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
TIMING REQUIREMENTS
(1) TCLCL
CLK Cycle Period
125
-
100
-
83
-
ns
(2) TCLCH
CLK Low Time
55
-
50
-
34
-
ns
(3) TCHCL
CLK High Time
40
-
37
-
34
-
ns
(4) TSVCH
Status Active Setup Time
35
-
35
-
35
-
ns
(5) TCHSV
Status Inactive Hold Time
10
-
10
-
5
-
ns
(6) TSHCL
Status Inactive Setup Time
35
-
35
-
35
-
ns
(7) TCLSH
Status Active Hold Time
10
-
10
-
5
-
ns
TIMING RESPONSES
(8) TCVNV
Control Active Delay
5
45
5
45
5
45
ns
1
(9) TCVNX
Control Inactive Delay
10
45
10
45
10
35
ns
1
(10) TCLLH
ALE Active Delay (from CLK)
-
20
-
20
-
20
ns
1
(11) TCLMCH
MCE Active Delay (from CLK)
-
25
-
23
-
23
ns
1
(12) TSVLH
ALE Active Delay (from Status)
-
20
-
20
-
20
ns
1
(13) TSVMCH
MCE Active Delay (from Status)
-
30
-
23
-
23
ns
1
(14) TCHLL
ALE Inactive Delay
4
18
4
18
4
18
ns
1
(15) TCLML
Command Active Delay
5
35
5
35
5
35
ns
2
(16) TCLMH
Command Inactive Delay
5
35
5
35
5
35
ns
2
(17) TCHDTL
Direction Control Active Delay
-
50
-
50
-
50
ns
1
(18) TCHDTH
Direction Control Inactive Delay
-
30
-
30
-
30
ns
1
(19) TAELCH
Command Enable Time (Note 1)
-
40
-
40
-
40
ns
3
(20) TAEHCZ
Command Disable Time
(Note 2)
-40-40
-40
ns
4
(21) TAELCV
Enable Delay Time
110
250
110
250
110
250
ns
2
(22) TAEVNV
AEN to DEN
-
25
-
25
-
25
ns
1
(23) TCEVNV
CEN to DEN, PDEN
-
25
-
25
-
25
ns
1
(24) TCELRH
CEN to Command
-
TCLML
+10
-
TCLML
-
TCLML
ns
2
(25) TLHLL
ALE High Time
TCLCH -
10
-
TCLCH -
10
-
TCLCH -
10
nns
1
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
1.5V
1.5V
VIL -0.4V
INPUT
VIH +0.4V
VOL
OUTPUT
VOH
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
C1
1
2.13V
220
80pF
2
2.29V
91
300pF
3
1.5V
187
300pF
4
1.5V
187
50pF
TEST
POINT
V1
C1 (SEE NOTE)
R1
OUTPUT FROM
DEVICE
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
82C88


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