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MR80C88-2B Datasheet(PDF) 8 Page - Intersil Corporation |
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MR80C88-2B Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 32 page  3-8 The BIU will automatically execute two fetch or write cycles for 16-bit operands. Certain locations in memory are reserved for specific CPU operations. (See Figure 2). Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to initial system initialization routine. Follow- ing RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed through its own pair of 16-bit pointers - segment address pointer and offset address pointer. The first pointer, used as the offset address, is loaded into the IP, and the second pointer, which designates the base address, is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts. Minimum and Maximum Modes The requirements for supporting minimum and maximum 80C88 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 80C88 is equipped with a strap pin (MN/MX) which defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX pin is strapped to GND, the 80C88 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX pins is strapped to VCC, the 80C88 generates bus control signals itself on pins 24 through 31 and 34. The minimum mode 80C88 can be used with either a muliplexed or demultiplexed bus. This architecture provides the 80C88 processing power in a highly integrated form. The demultiplexed mode requires one latch (for 64K addres- sability) or two latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 3). The 80C88 provides DEN and DT/R to control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode pro- vides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements. The maximum mode employs the 82C88 bus controller (See Figure 4). The 82C88 decode status lines S0, S1 and S2, and provides the system with all bus control signals. Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C88 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the 80C88 in maximum mode. These features allow coprocessors in local bus and remote bus configurations. TYPE 255 POINTER (AVAILABLE) RESET BOOTSTRAP PROGRAM JUMP TYPE 33 POINTER (AVAILABLE) TYPE 32 POINTER (AVAILABLE) TYPE 31 POINTER (AVAILABLE) TYPE 5 POINTER (RESERVED) TYPE 4 POINTER OVERFLOW TYPE 3 POINTER 1 BYTE INT INSTRUCTION TYPE 2 POINTER NON MASKABLE TYPE 1 POINTER SINGLE STEP TYPE 0 POINTER DIVIDE ERROR 16-BITS CS BASE ADDRESS IP OFFSET 014H 010H 00CH 008H 004H 000H 07FH 080H 084H FFFF0H FFFFFH 3FFH 3FCH AVAILABLE INTERRUPT POINTERS (224) DEDICATED INTERRUPT POINTERS (5) RESERVED INTERRUPT POINTERS (27) FIGURE 15. RESERVED MEMORY LOCATIONS 80C88 |
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